Source/Drain Silicon Structure for Shallow Junction Uniformity
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in scaling down transistor size due to issues with source/drain junction profile depth and thermal budget, which can lead to short-channel effects and transient-enhanced diffusion, while selective-epitaxial-growth processes result in thickness variations affecting electrical characteristics.
Innovation Solution
A method involving multiple ion implantations followed by rapid thermal anneal and epitaxial deposition/etching processes to form silicon-containing material structures with controlled thickness variations, reducing the thermal budget and minimizing damage to source/drain regions, and achieving uniform electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ion implantation and high thermal budget annealing are used to form source/drain regions, then dopant activation and damage repair are achieved, but junction profile depth becomes too deep and short-channel effects are aggravated
Solution Approach 1:
The patent changes the thermal parameter from high thermal budget to low thermal budget annealing (e.g., rapid thermal annealing at 700-900°C for short durations). This parameter change enables sufficient dopant activation and damage repair while limiting thermal diffusion that would otherwise deepen the junction profile and aggravate short-channel effects
Solution Approach 2:
The patent performs preliminary actions by forming offset spacers before ion implantation to define the source/drain region boundaries. This preliminary structuring allows precise control of dopant placement and junction depth, ensuring that activation occurs only in the intended regions without excessive deepening
2Length of moving object
If low thermal budget annealing is used to avoid deep junction profiles, then short-channel effects are minimized, but implantation damage may not be desirably cured
Solution Approach 1:
The patent optimizes the thermal parameters of rapid thermal annealing (temperature range 700-900°C, duration 1-30 seconds) to achieve the right balance: high enough temperature and sufficient duration to cure implantation damage, but low enough thermal budget to prevent excessive junction deepening and maintain short-channel effect control
Solution Approach 2:
The patent employs multiple sequential ion implantation steps (e.g., phosphorus then carbon, or arsenic then phosphorus) followed by annealing. This continuous process ensures thorough damage repair and dopant activation while maintaining precise control over the thermal exposure time, preventing junction profile deepening
3Ease of manufacture
If selective-epitaxial-growth is used to form silicon-containing material structures, then source/drain regions are formed, but thickness variations occur affecting electrical characteristics
Solution Approach 1:
The patent forms offset spacers as preliminary structures before epitaxial growth or ion implantation. These spacers serve as precise masks and thickness reference structures, ensuring uniform thickness of subsequently formed silicon-containing material structures across the chip, thereby reducing variations in electrical characteristics
Solution Approach 2:
The patent applies different processing conditions to different regions of the substrate by using offset spacers as local masks. This allows precise control of material deposition or implantation in specific areas, ensuring uniform thickness in critical regions while maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced thickness variations in silicon-containing material structures across the chip, leading to improved uniformity in electrical characteristics such as resistances and currents, while maintaining low thermal cycles to minimize dopant diffusion.
Implementation Method 1
Generally, a plurality of ion implantations have been implemented for forming source/drain (S/D) regions, lightly-doped drain (LDD) regions, and pocket regions of transistors
Implementation Method 2
After the multiple ion implantations, a rapid thermal anneal (RTA) is performed to activate dopants and to cure damage resulting from the ion implantations
Implementation Method 3
selective-epitaxial-growth (SEG) process has been proposed. For forming the S/D regions, the substrate near the gate electrodes is recessed. The SEG process epitaxially grows a single silicon layer in the recessed substrate
Data Source
AI summary
An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.