Source/Drain Region Layout to Confine Lateral Epitaxial Growth
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Solution Overview
Problem
Conventional transistors face issues with excessive lateral epitaxial growth of source/drain regions leading to epi-to-epi shorts and elevated parasitic capacitance, which degrade performance and increase power consumption, especially as device packing density increases.
Innovation Solution
The development of novel integrated circuit structures that confine lateral epitaxial growth of source/drain regions, ensuring self-alignment with channel wires and improved isolation, reducing parasitic capacitance and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial growth is used to form source/drain regions, then vertical growth is achieved, but excessive lateral growth occurs causing epi-to-epi shorts
Solution Approach 1:
A sacrificial material layer is introduced as an intermediary between adjacent channel wires. This sacrificial layer acts as a physical barrier that prevents lateral epitaxial growth from one source/drain region from contacting the adjacent channel wire and causing epi-to-epi shorts. The sacrificial material is subsequently removed after serving its protective function during the epitaxial growth process.
Solution Approach 2:
The sacrificial material layer is placed in advance between the channel wires before the epitaxial growth of source/drain regions. This preliminary action creates a protective barrier that preemptively prevents the harmful lateral growth from occurring, rather than attempting to correct the problem after epi-to-epi shorts have formed.
2Productivity
If device packing density is increased, then more devices per area are achieved, but parasitic capacitance increases degrading performance
Solution Approach 1:
The sacrificial material layer serves as an intermediary isolation structure between adjacent source/drain regions. By preventing direct lateral contact between epitaxially grown source/drain regions and adjacent channel wires, this intermediate layer reduces the parasitic capacitance that would otherwise form between closely spaced devices, enabling higher packing density without performance degradation.
3Reliability
If lateral spacing between transistors is increased to reduce epi-to-epi shorts, then short prevention is improved, but device isolation area increases
Solution Approach 1:
Instead of increasing lateral spacing between transistors to prevent epi-to-epi shorts, the invention introduces a vertical dimension solution by placing a sacrificial material layer between the channel wires. This allows devices to maintain close lateral spacing for high density while the vertical sacrificial layer provides the necessary isolation to prevent shorts during epitaxial growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These structures enhance device performance by minimizing epi-to-epi shorts and parasitic capacitance, allowing for denser device packing without increased resistance, thereby improving circuit efficiency and reducing power consumption.
Implementation Method 1
excessive lateral epitaxial growth of source/drain regions
Data Source
AI summary
Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.