Source/Drain Contact Structure With MCESL for Via Over-Etch Control
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Solution Overview
Problem
In the manufacturing of integrated circuits, there is a challenge in preventing over-etching during the formation of source/drain vias, which can lead to leakage current and reduced device performance due to the lack of effective etch stop layers and precise control over etching processes.
Innovation Solution
The implementation of a middle contact etch stop layer (MCESL) and doped regions in dielectric caps, which have different etch selectivities, slows down the etching process to prevent over-etching and ensures precise formation of via openings, thereby reducing the risk of leakage current and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used for source/drain via formation, then the etching process is simple and fast, but over-etching occurs leading to leakage current and reduced device performance
Solution Approach 1:
The patent applies preliminary action by forming the middle contact etch stop layer (MCESL) and doped regions in dielectric caps before the via etching process. These structures are prepared in advance to control the etching process and prevent over-etching, ensuring reliable device performance without requiring complex real-time control during etching
Solution Approach 2:
The patent introduces intermediary elements (MCESL and doped regions) that act as mediators between the etching process and the underlying structures. These intermediaries control the etching rate and provide etch stop functionality, preventing direct over-etching of critical structures while maintaining a relatively simple overall process
2Reliability
If no etch stop layers are used, then the manufacturing process is simple, but over-etching occurs causing leakage current
Solution Approach 1:
The patent segments the etch stop functionality into multiple distinct components: the middle contact etch stop layer (MCESL) and doped regions in dielectric caps. This segmentation allows each component to perform specific functions in the etching process, providing precise control over etching depth and preventing over-etching while maintaining manageable structural complexity
Solution Approach 2:
The patent applies local quality by creating doped regions with different etch selectivities at specific locations within the dielectric caps. These locally modified regions provide targeted etch stop functionality where needed, preventing over-etching at critical interfaces while keeping the overall structure relatively simple
3Manufacturing precision
If etching process is not precisely controlled, then the manufacturing process is fast and simple, but via opening formation is inaccurate leading to performance degradation
Solution Approach 1:
The patent uses preliminary action by pre-forming the MCESL and doped regions to establish precise etching boundaries before the via etching process. This preliminary preparation enables accurate via opening formation without requiring complex real-time etching control, maintaining manufacturing efficiency while achieving high precision
Solution Approach 2:
The patent implements feedback through the etch stop layers that provide inherent control signals during the etching process. When the etching front reaches the MCESL or doped regions, the change in etch rate or complete stop provides feedback that automatically limits etching depth, ensuring precise via opening formation without over-etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents over-etching, reduces the risk of leakage current, and enhances the electrical characteristics of integrated circuits by ensuring accurate and controlled formation of source/drain vias.
Implementation Method 1
The implementation of a middle contact etch stop layer (MCESL) and doped regions in dielectric caps, which have different etch selectivities, slows down the etching process to prevent over-etching
Data Source
AI summary
A method includes forming a source/drain contact over a source/drain region. An ion implantation process is performed to form a doped region in a top of the source/drain contact. After the ion implantation process is performed, an interlayer dielectric (ILD) layer is deposited to cover the doped region of the source/drain contact. The ILD layer is etched to form a via opening exposing the source/drain contact. A source/drain via is filled in the via opening.