Source-Drain Structure for Non-Volatile Memory Disturbance Reduction
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Solution Overview
Problem
The reliability of flash memory devices is limited by drain disturbance in flash memory arrays due to high drain bias, which causes soft-write operations and reduces the quality of tunnel oxide, leading to charge loss in programmed cells.
Innovation Solution
A source-drain structure with a lightly-doped ultra-shallow junction and a heavily-doped region, where the drain-substrate junction has a smaller edge curvature and lower impurity ion concentration than the heavily-doped region, reducing the maximum electric field and hot carrier generation, and a method involving ion implantation to form these regions with specific angles and energies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high drain bias is applied during programming operation, then programming speed is improved, but drain disturbance increases and tunnel oxide quality deteriorates
Solution Approach 1:
The patent applies local quality by creating a lightly-doped ultra-shallow junction specifically at the drain-substrate interface region, while maintaining heavily-doped regions elsewhere in the drain. This localized doping differentiation reduces the maximum electric field at the critical drain-substrate junction where hot carrier generation occurs, thereby suppressing drain disturbance and protecting tunnel oxide quality while allowing high drain bias to be maintained for fast programming.
Solution Approach 2:
The patent changes the doping parameter (impurity concentration) by creating a gradient from heavily-doped regions to a lightly-doped ultra-shallow junction at the drain-substrate interface. This parameter change reduces the maximum electric field strength at the critical junction, suppressing hot carrier generation and drain disturbance effects while maintaining the ability to apply high programming voltages.
2Reliability
If high channel doping level is used to prevent cell punch-through, then programming reliability is improved, but hot electron effect increases and drain disturbance worsens
Solution Approach 1:
The patent applies local quality by maintaining high channel doping levels throughout most of the channel to prevent punch-through, while creating a localized lightly-doped ultra-shallow junction at the drain-substrate interface. This spatial differentiation allows the channel to remain highly doped for reliability while the critical junction region remains lightly doped to suppress hot electron generation.
Solution Approach 2:
The patent segments the drain region into functionally distinct zones: a heavily-doped channel region for punch-through prevention, and a lightly-doped ultra-shallow junction at the substrate interface for hot carrier suppression. This segmentation allows each region to be optimized for its specific function without compromising the other.
3Measurement precision
If long pulse time is used during read operation, then read accuracy is improved, but soft-write operation occurs and memory cell state changes
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the drain-substrate junction with a lightly-doped ultra-shallow junction before read operations occur. This preliminary structural preparation reduces the maximum electric field at the drain-substrate interface, thereby preventing soft-write effects during extended read operations and maintaining memory cell state stability even with longer pulse times required for high read accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces drain and read disturbances, allowing for higher operating voltages without compromising programming speed, thereby enhancing the reliability and performance of flash memory devices.
Implementation Method 1
a method involving ion implantation to form these regions with specific angles and energies
Implementation Method 2
reducing the maximum electric field and hot carrier generation
Implementation Method 3
the high channel doping level results in a relatively steep doping distribution at the drain junction, that generates a tunneling effect, to thereby stimulate hot electron effect
Data Source
AI summary
A source-drain structure and method of manufacturing the same are disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.