FinFET Source/Drain Layering for Short-Free Region Merging
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density and reducing feature sizes while avoiding electric shorts and contact resistance in FinFET manufacturing, particularly in forming source/drain regions with existing lithography and epitaxial growth techniques.
Innovation Solution
The use of epitaxial growth techniques with an intermediate source/drain layer to increase merge heights and create larger air gaps underneath source/drain regions, allowing for the merging of neighboring regions without electric shorts and achieving flat top profiles for reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithography and epitaxial growth techniques are used to form source/drain regions, then manufacturing process simplicity is maintained, but electric shorts between neighboring source/drain regions occur and contact resistance increases
Solution Approach 1:
The source/drain region formation is segmented into multiple sequential epitaxial growth steps, where each step deposits a specific layer with controlled thickness and composition. This segmentation allows precise control over the vertical profile and merging behavior of neighboring source/drain regions, preventing electric shorts while maintaining manufacturing feasibility through standardized epitaxial processes
Solution Approach 2:
The patent employs parameter changes in the epitaxial growth process, including varying temperature, pressure, gas flow rates, and precursor ratios across different growth steps. These parameter adjustments enable control over the growth rate, layer composition, and surface morphology, achieving flat top profiles and appropriate merge heights to eliminate electric shorts and reduce contact resistance
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but electric shorts and contact resistance problems worsen
Solution Approach 1:
The patent addresses the two-dimensional scaling limitations by introducing precise three-dimensional control through multi-layer epitaxial growth. By controlling the vertical dimensions (layer thicknesses, merge heights, and air gap formation) independently of lateral feature size reduction, the invention enables continued integration density improvement while maintaining electrical performance through controlled source/drain region merging and flat top profile formation
3Reliability
If source/drain regions are merged to reduce gate to source/drain capacitance, then AC performance improves, but electric shorts between neighboring regions may occur
Solution Approach 1:
The patent applies local quality by creating spatially varying source/drain region structures through selective epitaxial growth. Different regions of the source/drain structure have different properties: the merged regions provide low capacitance for improved AC performance, while the controlled air gaps and isolation structures in specific locations prevent electric shorts. This local differentiation allows simultaneous optimization of electrical performance and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced gate to source/drain capacitance and improved AC performance of FinFETs by enabling a good process window for merging source/drain regions without undesired shorts and providing flat top profiles for lower contact resistance.
Implementation Method 1
forming a second layer on the first layer by flowing a silane gas
Implementation Method 2
forming a third layer on the second layer, the forming the third layer including a cyclic deposition-etch process, the third layer being a single continuous material extending from one recess to the other
Data Source
AI summary
A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.