Source/Drain Pattern Layout for Integrated Semiconductor Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, reliability, and multi-functionality due to limitations in the design and structure of source/drain patterns, which affect electrical characteristics.
Innovation Solution
The semiconductor devices incorporate variously shaped source/drain patterns with specific configurations, including merged and spaced parts, and unique valley formations between these parts, along with a device isolation layer and gate electrodes, to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain patterns are used, then manufacturing is simpler, but electrical characteristics are insufficient
Solution Approach 1:
The source/drain pattern is divided into multiple segments including a first source/drain part, a second source/drain part, and a connection part. Each segment serves a specific function: the first and second parts provide electrical contact on different active patterns, while the connection part bridges them. This segmentation allows optimization of electrical characteristics for each segment while maintaining overall functionality.
Solution Approach 2:
Different portions of the source/drain pattern are designed with different geometries and positions to optimize local electrical characteristics. The connection part has a specific shape that extends along an upper portion of the first active pattern, creating localized electric field distributions that improve carrier injection and transport. The device isolation layer is positioned at specific depths to control electric fields in different regions.
Solution Approach 3:
The source/drain pattern utilizes three-dimensional positioning with the connection part extending along an upper portion of the first active pattern at a higher elevation. The device isolation layer is positioned below the source/drain pattern at a specific depth, creating vertical layering that adds a depth dimension to the electrical field control, enabling improved carrier transport pathways.
2Productivity
If device integration is increased, then functionality and speed improve, but manufacturing precision requirements increase
Solution Approach 1:
Multiple source/drain parts and connection parts are merged into a single continuous conductive structure formed by selective epitaxial growth. This merging approach ensures precise alignment between different segments since they are created as an integrated structure rather than separate components requiring alignment, thus maintaining manufacturing feasibility while achieving high device integration.
Solution Approach 2:
The device isolation layer is formed and positioned at a predetermined depth before the source/drain pattern is fully formed. This preliminary positioning of the isolation layer establishes reference planes and depth markers that guide subsequent epitaxial growth and patterning steps, ensuring precise alignment of the source/drain structures with the underlying active patterns and isolation structures.
Data Source
AI summary
A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.