Source/Drain Layer Profile Control in Multi-Bridge Channel Transistors
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Solution Overview
Problem
The existing processes for forming source/drain layers in semiconductor devices, particularly in multi-bridge channel transistors, often result in complex profiles and require selective epitaxial growth, which can lead to inefficiencies and difficulties in achieving optimal device performance.
Innovation Solution
A method involving ion implantation and annealing processes to form source/drain layers with specific profiles, avoiding selective epitaxial growth, and using silicon germanium doped with P-type impurities for PMOS transistors and silicon doped with N-type impurities for NMOS transistors, allowing for simpler and more efficient manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective epitaxial growth is used to form source/drain layers, then manufacturing precision can be improved, but device complexity and process difficulty increase
Solution Approach 1:
The patent changes the formation method parameters from selective epitaxial growth to ion implantation followed by annealing. This parameter change achieves the desired source/drain layer profile (constant inclination sidewall) while avoiding the complexity of selective epitaxial growth processes, including multiple doping steps and precise temperature control requirements.
Solution Approach 2:
The patent replaces the chemical growth mechanism of selective epitaxial growth with a physical ion implantation process followed by thermal annealing. This substitution simplifies the manufacturing process by using well-established ion implantation technology instead of complex selective epitaxial growth, reducing process difficulty while maintaining manufacturing precision.
2Reliability
If selective epitaxial growth is used to form source/drain layers, then electrical characteristics can be improved, but productivity decreases due to process time and complexity
Solution Approach 1:
The patent performs preliminary ion implantation of dopants into the source/drain regions before final annealing. This preliminary action ensures proper dopant distribution and activation, achieving excellent electrical characteristics while streamlining the overall process by combining doping and formation steps, thereby improving manufacturing efficiency.
Solution Approach 2:
The patent changes from a multi-step selective epitaxial growth process to a simplified ion implantation and annealing sequence. This parameter change reduces total process time and steps while maintaining or improving electrical characteristics through precise control of ion energy, dose, and annealing temperature, thus enhancing both reliability and productivity.
3Reliability
If complex profiles are formed in source/drain layers, then device performance can be optimized, but ease of manufacture deteriorates
Solution Approach 1:
The patent achieves the desired source/drain layer profile with constant inclination sidewall through controlled ion implantation parameters (energy, angle, dose) and annealing conditions. This parameter-based approach creates the complex-appearing profile through simple, well-controlled physical processes, maintaining ease of manufacture while optimizing device performance.
Solution Approach 2:
The patent replaces complex selective epitaxial growth processes with straightforward ion implantation and annealing. This substitution achieves the required source/drain layer morphology through simple, repeatable physical processes that are easier to manufacture with standard equipment, improving ease of manufacture while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with improved electrical characteristics by creating source/drain layers with controlled profiles, enhancing device performance and simplifying the manufacturing process.
Implementation Method 1
A method involving ion implantation and annealing processes to form source/drain layers
Implementation Method 2
A method involving ion implantation and annealing processes to form source/drain layers
Data Source
AI summary
A semiconductor device including a substrate extending in a first direction and a second direction perpendicular to the first direction, a first active pattern protruding from a top surface of the substrate and extending in the first direction, an isolation pattern covering a sidewall of the first active pattern on the substrate, first silicon patterns spaced apart from each other in a third direction on the first active pattern, the third direction perpendicular to the first direction and second direction, a first source/drain layer extending in the third direction from a top surface of the first active pattern on the first active pattern, and in contact with sidewalls of the first silicon patterns, wherein a sidewall of the first source/drain layer in the second direction has a constant inclination with respect to the top surface of the substrate, and a gate structure extending in the second direction while filling a gap between the first silicon patterns on the substrate.