Endpoint-Controlled Source/Drain Recess Etching for Transistor Stress
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Solution Overview
Problem
The etching process for forming source/drain regions in electronic devices, particularly on silicon-on-insulator substrates, faces challenges such as surface loading effects and recess variations due to timed etches and protective layer removal, which can damage exposed transistor locations.
Innovation Solution
The use of a plurality of protective layers with an end-point-termination technique to control the depth of recesses in PMOS transistor source/drain regions, where one layer is etched simultaneously with the source/drain locations at a controlled rate, reducing loading effects and allowing for uniformity and greater control in recess formation, followed by epitaxial layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If timed etches with protective layers are used to form source/drain regions, then the etching process can be performed on NMOS and PMOS transistors independently, but surface loading effects cause locally increased etch rates that result in recess variations
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material between the protective layer and the source/drain regions. This sacrificial layer etches at a controlled rate that matches the source/drain etch rate, serving as a reference for endpoint detection. The intermediary layer enables precise control of recess depth by allowing the etch process to be terminated when the sacrificial layer is completely removed, thereby eliminating loading effects and achieving uniform recesses across the wafer.
2Device complexity
If timed etches are used to form source/drain recesses, then the etching process can be simplified, but loading effects during etching cause locally increased etch rates that are hard to control
Solution Approach 1:
The etching process incorporates real-time feedback through endpoint detection. The etch rate is monitored by detecting when the sacrificial layer is completely removed, which signals that the source/drain recesses have reached the desired depth. This feedback mechanism allows dynamic adjustment of the etching process, compensating for loading effects and ensuring uniform etch rates across the entire wafer surface.
3Reliability
If protective layers are removed after etching source/drain regions, then the protective function is achieved, but the exposed transistor locations are further subjected to chemistries that can damage them
Solution Approach 1:
The sacrificial layer serves as an intermediary that remains throughout the etching process, protecting the source/drain regions from direct exposure to harmful chemistries. After the etching is complete and the sacrificial layer is removed, the protective layer can be safely removed without damaging the transistor locations, as the harmful chemistries are no longer present in the process.
4Device complexity
If conventional etching methods are used for source/drain regions, then the process is simpler, but recess variations occur that can result in bottoming-out with thin active layers
Solution Approach 1:
The conventional timed etching method is replaced with an endpoint-detection-based etching method. Instead of relying on predetermined etch times, the process uses real-time monitoring of the sacrificial layer removal to dynamically control the etching duration. This substitution of the control mechanism enables precise recess depth control, preventing bottoming-out of thin active layers while maintaining process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides more controlled and uniform source/drain recesses, reduces damage to exposed transistor locations during protective layer removal, and enables precise epitaxial layer formation with compressive or tensile stress for improved transistor performance.
Implementation Method 1
The etch of source/drain regions can be used to clean source/drain regions or to form recesses within which subsequent epitaxial layer can be formed
Implementation Method 2
epitaxially formed source/drain regions
Data Source
AI summary
An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.