Source/Drain Contact Recess Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become increasingly integrated, parasitic capacitance between the source/drain contact and the gate electrode leads to performance degradation, particularly due to further recessing of the source/drain contact in regions without epitaxial layers, exacerbating AC performance issues.
Innovation Solution
The semiconductor device incorporates a first source/drain contact with a shallower recess in the intermediate region and a second source/drain contact with a deeper recess in the power supply region, reducing parasitic capacitance and improving electrical resistance by optimizing the contact geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the source/drain contact is further recessed in regions without epitaxial layers to reduce parasitic capacitance, then parasitic capacitance is reduced, but AC performance deteriorates
Solution Approach 1:
The patent applies local quality by creating different recess depths in different regions of the source/drain contact. Specifically, the contact has a first recess depth in the intermediate region and a second recess depth in the power supply region, allowing each region to be optimized for its specific function while maintaining overall AC performance.
Solution Approach 2:
The source/drain contact is segmented into multiple regions with different recess characteristics. The contact includes an intermediate region with a first recess portion and a power supply region with a second recess portion, enabling differentiated treatment of different contact regions to balance parasitic capacitance reduction with AC performance maintenance.
2Object-generated harmful factors
If the source/drain contact is recessed to reduce parasitic capacitance, then parasitic capacitance is reduced, but electrical resistance increases
Solution Approach 1:
Different recess depths are applied to different regions: the intermediate region has a first recess depth optimized for reducing parasitic capacitance, while the power supply region has a second recess depth optimized for maintaining low electrical resistance. This local differentiation resolves the contradiction between reducing parasitic capacitance and maintaining electrical conductivity.
Data Source
AI summary
A semiconductor device includes a substrate having a first power supply region, a second power supply region, and a cell region therein. The cell region extends between the first power supply region and the second power supply region. A first active region and a second active region are provided, which extend side-by-side within the cell region. A first power supply wiring is provided, which extends in the first direction within the first power supply region. A first source/drain contact is provided, which connects the first active region and the second active region. A second source/drain contact is provided, which connects the first active region and the first power supply wiring. The first source/drain contact includes a first recess portion disposed inside an intermediate region between the first active region and the second active region.