FinFET Source/Drain Recess Shaping for Low-Leakage Performance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in forming source/drain regions with reduced defects and improved performance, such as high on-current and low leakage current, while maintaining integration density and preventing drain-induced barrier lowering effects.
Innovation Solution
The formation of improved source/drain regions involves etching recesses in semiconductor fins using an anisotropic etch process, removing etching residue with ammonia-based etching, and expanding the recesses using hydrogen-based plasma etching to create V-shaped surfaces extending under gate spacers, which allows for greater dopant diffusion and reduced electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and defect control become more difficult
Solution Approach 1:
The patent applies preliminary action by performing multiple etching steps (first anisotropic etch, then isotropic etch) to progressively form the source/drain regions. The first etch creates the basic structure, and the second etch refines it by removing residue and forming the final shape, ensuring high precision at reduced feature sizes
Solution Approach 2:
The etching process is segmented into multiple distinct steps: a first anisotropic etch process to create initial recesses, followed by a second isotropic etch process to remove residue and refine the structure. This segmentation allows each step to be optimized for its specific function, improving overall manufacturing precision
2Ease of manufacture
If conventional etching processes are used to form source/drain regions, then manufacturing is simpler, but etching residue remains and device defects increase
Solution Approach 1:
The etching process is divided into two segments: a first anisotropic etch process that creates the initial source/drain region structure, and a second isotropic etch process that removes etching residue and refines the structure. This segmentation eliminates residue accumulation while maintaining manufacturing feasibility
Solution Approach 2:
The patent converts the potentially harmful effect of etching residue into a beneficial process sequence. The first etch creates the structure, and the second etch specifically targets and removes the residue that would otherwise cause defects. This transforms the residue problem into a controlled process step
3Ease of manufacture
If source/drain regions are formed without extending under gate spacers, then manufacturing is easier, but dopant diffusion is limited and electrical resistance remains high
Solution Approach 1:
The patent uses preliminary action by first forming gate spacers, then using them as etch stops during the source/drain region formation. The etching process is controlled to extend precisely to the gate spacer boundaries, creating the optimal geometry for dopant diffusion while maintaining manufacturing control
Solution Approach 2:
The source/drain regions are formed with different geometries in different locations: they extend under the gate spacers to maximize dopant diffusion and reduce resistance, while the gate spacers themselves maintain their protective function. This local optimization of geometry achieves both low resistance and ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with enhanced Ion-Ioff performance, reduced drain-induced barrier lowering effects, and decreased device defects, leading to improved overall device performance.
Implementation Method 1
etching recesses in semiconductor fins using an anisotropic etch process
Implementation Method 2
removing etching residue with ammonia-based etching
Implementation Method 3
expanding the recesses using hydrogen-based plasma etching
Data Source
AI summary
A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.