Multi-Channel Source/Drain Structure for Short-Channel Suppression
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing performance and reliability, particularly in scaling techniques for multi-gate transistors, where the short channel effect and current control are not adequately addressed.
Innovation Solution
The semiconductor device incorporates a multi-channel active pattern with gate structures, a semiconductor liner layer, and a source/drain pattern featuring silicon-germanium layers and insertion layers with saddle structures, which improve current control and reduce the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used for scaling, then degree of integration is improved, but short channel effect becomes more severe
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FinFET, nanowire, nanosheet) that wrap around the channel in multiple directions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects while enabling higher device integration density.
Solution Approach 2:
The patent implements nested multi-gate structures where multiple channel layers are stacked vertically (nanosheets) or arranged in three-dimensional configurations (nanowires surrounded by gates). These nested structures allow multiple active channels to occupy a small footprint area, significantly increasing the degree of integration while maintaining effective gate control over each channel.
2Reliability
If gate length is increased to suppress short channel effect, then reliability is improved, but current control capability deteriorates
Solution Approach 1:
Instead of increasing gate length in the planar direction, the patent employs multi-gate structures that provide electrostatic control from multiple directions (top, bottom, and sidewalls). This three-dimensional gate configuration suppresses short channel effects without requiring longer channel lengths, thereby maintaining high current control capability and device speed.
3Reliability
If complex multi-layer source/drain structure is implemented, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs selective epitaxial growth to form the multi-layer source/drain structure. The epitaxial process automatically conformally deposits each layer (semiconductor liner layer, first semiconductor insertion layer, second semiconductor insertion layer, semiconductor filling layer) onto the underlying structure, ensuring precise thickness control and automatic alignment with previous layers without requiring additional lithographic alignment steps.
Solution Approach 2:
The patent utilizes controlled epitaxial growth parameters (temperature, pressure, gas flow rates, precursor ratios) to precisely control the thickness, composition, and crystalline quality of each source/drain layer. By adjusting these parameters, the manufacturing process achieves the required precision for complex multi-layer structures while maintaining device performance.
Data Source
AI summary
A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.