3D Source/Drain Separation Layout for Dense Semiconductor Contacts
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to the need for higher integration density, which requires finer patterns with narrower widths and closer spacing distances. Additionally, the reduction in size of metal oxide semiconductor FETs has limited their operating properties, necessitating the development of semiconductor devices with three-dimensional transistor structures.
Innovation Solution
A semiconductor device is designed with a first lower separation pattern having a first portion with a first lower separation region and a first upper separation region. Source/drain patterns are placed on both sides of the first upper separation region, and a common source/drain contact plug electrically connects these patterns. Conductive vias and wiring patterns are also integrated to enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to meet demand for high-performance semiconductor devices, then productivity and functionality are improved, but manufacturing precision and pattern quality deteriorate due to finer widths and closer spacing distances
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFET structures to three-dimensional vertically stacked transistor structures. Multiple channel regions are stacked vertically to increase integration density without further reducing lateral pattern dimensions, thereby maintaining manufacturing precision while achieving higher productivity.
Solution Approach 2:
The separation pattern is divided into multiple segments including lower separation regions, upper separation regions, and side separation regions. This segmentation allows each region to be optimized independently for its specific function, improving overall pattern quality while enabling higher integration density through efficient space utilization.
2Productivity
If size of metal oxide semiconductor FET is reduced to increase integration density, then productivity is improved, but operating properties deteriorate
Solution Approach 1:
The patent employs vertically stacked channel regions arranged in three dimensions rather than lateral expansion. This allows the transistor effective channel width to be increased through vertical stacking while maintaining compact lateral footprint, thus improving operating properties without sacrificing integration density.
Solution Approach 2:
The patent uses composite material structures including semiconductor layers, gate electrodes, and separation patterns with different material properties. This enables optimization of electrical characteristics through material composition while maintaining the compact three-dimensional structure required for high integration density.
3Productivity
If finer patterns with narrower widths and closer spacing are implemented to increase integration density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent organizes multiple channel regions and separation patterns in a systematic vertical stack configuration. This three-dimensional arrangement, while physically complex, follows regular repeating patterns that simplify the manufacturing process and reduce the number of unique pattern elements required, thereby managing device complexity.
Solution Approach 2:
The separation pattern serves multiple functions simultaneously: it electrically isolates adjacent transistor regions, provides structural support for vertical stacking, and defines the geometric boundaries of channel regions. This multi-functionality reduces the need for additional separate structures, simplifying the overall device architecture despite the three-dimensional configuration.
Data Source
AI summary
A semiconductor device may include a first lower separation pattern including a first portion, the first portion including a first lower separation region and a first upper separation region on the first lower separation region; a first source/drain pattern and a second source/drain pattern on both sides of the first upper separation region; a common source/drain contact plug on the first and second source/drain patterns and the first upper separation region, and electrically connected to the first and second source/drain patterns; a first conductive via electrically connected to the common source/drain contact plug and on the common source/drain contact plug; and a first wiring pattern electrically connected to the first conductive via and on the first conductive via.