Source/Drain Contact Structure With SiGe Cover Layer
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Solution Overview
Problem
As semiconductor devices downscale, the reduction in contact size leads to increased contact resistance, deteriorating electrical performance such as speed and power due to higher resistance.
Innovation Solution
The integration of a cover semiconductor layer, specifically silicon germanium, on the source/drain area, along with a spacer and interlayer insulating film, reduces contact resistance by improving ohmic contact characteristics and increasing carrier concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of contacts is reduced to match downscaling of semiconductor devices, then the device size is reduced, but contact resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent changes the material composition of the contact by introducing a cover semiconductor layer with different compositional parameters (e.g., silicon germanium with varying Ge concentrations) to optimize electrical properties. This allows reducing contact size while maintaining low contact resistance through compositional optimization rather than size increase.
Solution Approach 2:
The patent employs a composite structure consisting of a cover semiconductor layer formed on the source/drain area, where the layer comprises multiple materials with different properties (e.g., silicon germanium layer over silicon). This composite approach enables the contact to achieve both small size and low resistance by combining the advantages of different materials.
2Volume of moving object
If the contact size is reduced, then device miniaturization is achieved, but ohmic contact characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating a cover semiconductor layer with specific material properties only in the contact region. The layer has localized compositional gradients (e.g., varying germanium concentration) that are tailored specifically to improve ohmic contact characteristics at the contact interface, while other regions of the device maintain their original structure.
Solution Approach 2:
The patent modifies local parameters of the semiconductor material in the contact region by introducing a cover layer with controlled compositional parameters. The germanium concentration and layer thickness are precisely controlled to optimize ohmic contact properties, enabling reliable electrical contact despite reduced contact dimensions.
3Ease of manufacture
If traditional silicon-based contacts are used, then manufacturing is simpler, but contact resistance is higher
Solution Approach 1:
The patent performs preliminary action by forming the cover semiconductor layer on the source/drain area before creating the contact structure. This pre-formed layer is prepared in advance with optimized material composition and thickness, so that when the contact is subsequently formed, low resistance is already achieved without requiring complex post-processing steps.
Solution Approach 2:
The cover semiconductor layer acts as an intermediary between the traditional silicon-based source/drain area and the contact structure. This intermediate layer mediates the electrical contact properties, providing a transition region that reduces contact resistance while maintaining compatibility with standard silicon manufacturing processes.
Data Source
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AI summary
An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.