Source/Drain Contact Structure With SiGe Layer for Lower Resistance
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Solution Overview
Problem
As semiconductor devices downscale, the reduction in contact size leads to increased contact resistance, deteriorating electrical performance such as speed and power performance due to higher resistance.
Innovation Solution
The integration of a cover semiconductor layer, specifically silicon germanium, on the source/drain area with a gate stack and spacers, along with an interlayer insulating film, reduces contact resistance by improving ohmic contact characteristics through increased carrier concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of contacts is reduced to match downscaling of semiconductor devices, then device integration is improved, but contact resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent changes the material parameter of the contact structure by introducing a cover semiconductor layer (e.g., silicon germanium) with different electrical properties than traditional silicon. This material parameter change increases carrier concentration at the contact interface, thereby reducing contact resistance despite the reduced contact size. The cover semiconductor layer acts as an intermediate layer that modifies the electrical characteristics of the contact region.
Solution Approach 2:
The patent employs a composite contact structure consisting of multiple materials: the traditional silicon substrate, a cover semiconductor layer (such as silicon germanium alloy), and the contact electrode itself. This composite structure combines the advantages of different materials - the silicon provides mechanical support and basic electrical properties, while the cover semiconductor layer enhances carrier concentration and reduces contact resistance, creating a multi-material contact system that overcomes the limitations of single-material contacts at scaled dimensions.
2Quantity of substance
If the size of individual microcircuit patterns decreases, then device density is improved, but contact resistance increases and electrical performance deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the material composition and carrier concentration in the contact region through the cover semiconductor layer. This allows the contact to maintain low resistance even when the overall device size and contact dimensions are reduced to achieve higher device density. The cover semiconductor layer's higher carrier concentration compensates for the reduced contact area, preserving electrical performance.
Solution Approach 2:
The patent applies local quality by introducing the cover semiconductor layer specifically at the contact region rather than throughout the entire device. This localized modification targets only the area where electrical contact is made, enhancing carrier concentration and reducing contact resistance at that specific location while leaving the rest of the device structure unchanged, thus achieving high device density without compromising electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases contact resistance by approximately 20% compared to traditional silicon-based contacts, enhancing electrical performance in terms of speed and power.
Implementation Method 1
reduces contact resistance by improving ohmic contact characteristics through increased carrier concentration
Data Source
AI summary
An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.