Source/Drain Contact Interface With Germanium-Rich SiGe Layer
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Solution Overview
Problem
Integrated circuits face significant inefficiencies and energy losses due to parasitic effects, particularly at the interface between source/drain features and contacts, which increase resistance and lead to excess heat, reduced operating frequency, and potential device failure, especially in FinFETs with silicon-germanium alloy semiconductors.
Innovation Solution
A method is introduced to form a germanium-rich layer at the top of source/drain features through controlled oxidation, reducing resistance at the interface with contacts without additional epitaxial deposition or implantation processes, thereby improving the interface quality selectively for SiGe-containing devices without affecting Si-containing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional epitaxial deposition or implantation processes are used to form a germanium-rich layer, then the interface quality and contact resistance can be improved, but the manufacturing complexity and process time increase
Solution Approach 1:
The patent extracts and removes the oxide layer formed on the source/drain feature through selective oxidation, thereby obtaining a germanium-rich layer without requiring additional epitaxial deposition or implantation processes. This extraction approach simplifies the manufacturing process while achieving the desired interface quality improvement.
Solution Approach 2:
The patent converts the harmful oxide layer, which would normally increase resistance, into a beneficial process step. By selectively oxidizing and then removing the oxide layer, the process inadvertently creates a germanium-rich layer that improves interface quality and reduces contact resistance, turning a potential defect into an advantage.
2Productivity
If the interface size between conductive features and circuit features is reduced to increase device density, then production efficiency increases, but parasitic resistance at the interface increases
Solution Approach 1:
The patent applies local quality by creating a germanium-rich layer specifically at the interface region where contacts meet the source/drain features. This localized modification of material composition addresses the resistance problem only where it occurs, without affecting other parts of the device, thereby maintaining high device density while improving interface quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The germanium-rich layer effectively lowers contact resistance and enhances the quality of the source/drain interface, improving the performance and reliability of integrated circuits by reducing energy losses and heat generation.
Implementation Method 1
The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature
Data Source
AI summary
Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.