Source/Drain Silicide Layout for Stacked GAA Contact Resistance
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Solution Overview
Problem
As gate-all-around (GAA) devices continue to scale, the addition of multiple stacked channel layers degrades their performance, particularly due to increased complexity and challenges in maintaining effective gate control and reducing short-channel effects.
Innovation Solution
The method involves forming a multigate device with multiple voids in the source/drain region, where a first semiconductor layer stack and a second semiconductor layer stack are formed over a substrate, with inner spacers along the sidewalls of the first semiconductor layers, and facets with a (111) crystallographic orientation are etched to promote epitaxial growth of source/drain features with voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stacked channel layers are added to GAA devices to improve performance, then gate control and short-channel effects are improved, but device performance degrades due to increased complexity
Solution Approach 1:
The source/drain region is segmented into multiple discrete contact openings at different vertical levels, allowing independent access to different channel layers. This segmentation enables selective contact formation that simplifies the overall device structure while maintaining effective gate control across multiple stacked channels.
Solution Approach 2:
The patent transitions from planar contact formation to three-dimensional vertical contact formation. Contact openings are formed at different vertical levels (first level and second level) to access different channel layers, adding a vertical dimension to the contact architecture that resolves the complexity issue while maintaining gate control.
2Ease of manufacture
If conventional source/drain contact formation is used in scaled GAA devices, then manufacturing is simplified, but parasitic resistances and capacitances increase
Solution Approach 1:
The patent performs preliminary etching to form contact openings that expose voids in the source/drain region before final contact formation. This preliminary action of creating void-exposing openings allows subsequent silicide filling to occur in optimized locations, reducing parasitic resistances without requiring complex post-processing steps.
Solution Approach 2:
The source/drain region incorporates voids (porous structures) that are strategically exposed through contact openings. These voids reduce parasitic capacitances between the source/drain region and surrounding structures, while the silicide filling process targets these void regions to minimize parasitic resistances.
3Manufacturing precision
If stronger etching processes are used to form contact openings, then contact formation is improved, but punch-through leakage occurs
Solution Approach 1:
The etching process is applied locally and selectively to specific regions where contact openings are needed, rather than using aggressive global etching. The etch selectively removes material to expose voids in the source/drain region while preserving the integrity of channel regions, preventing punch-through leakage while achieving precise contact formation.
Solution Approach 2:
The patent uses voids in the source/drain region as intermediary structures that facilitate contact formation. These voids serve as natural etch stop points and contact targets, allowing gentle etching to reach the desired contact depth without penetrating through the channel, thereby preventing punch-through while ensuring proper contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances contact formation and improves the performance of multigate devices by reducing parasitic resistances and capacitances, while avoiding stronger etching processes that could lead to punch-through leakage.
Implementation Method 1
facets with a (111) crystallographic orientation are etched to promote epitaxial growth of source/drain features with voids
Data Source
AI summary
Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.