Source/Drain Contact Structure With Single Inner Spacer
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Solution Overview
Problem
In semiconductor manufacturing, the use of dual inner spacers in source/drain contacts and single spacers in gate contacts can lead to high contact resistance and electrical shorts due to Silicon Nitride (SiN) seam voids formed during atomic layer deposition, which reduces circuit performance.
Innovation Solution
Implementing a semiconductor design with a single inner spacer in source/drain contacts and no spacer in gate contacts, utilizing two seamless dielectric layers - an oxide-based and a nitride-based layer - to prevent electrical shorts and enhance circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual inner spacers are used in source/drain contacts, then the possibility of short between CA and CB is reduced, but contact resistance increases and circuit performance decreases
Solution Approach 1:
The patent applies different spacer configurations to different contact types: source/drain contacts use a single inner spacer while gate contacts use no inner spacer. This local differentiation allows optimization for each contact type's specific requirements, reducing overall contact resistance while maintaining short prevention where critical.
2Manufacturing precision
If single inner spacer is used in source/drain contact, then contact resistance is reduced and circuit performance is improved, but the possibility of short between CA and CB increases
Solution Approach 1:
The patent implements local quality by applying single inner spacer configuration specifically to source/drain contacts where low contact resistance is critical for performance, while using no inner spacer for gate contacts. This targeted approach optimizes each contact type for its primary function.
Solution Approach 2:
The patent segments the contact structure into different types (source/drain vs. gate contacts) with different spacer configurations. This segmentation allows each contact type to be independently optimized, with source/drain contacts using single spacers for low resistance and gate contacts using no spacers for other performance characteristics.
3Reliability
If seamless dielectric layers are implemented, then electrical shorts are prevented and circuit performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent uses composite dielectric structures with multiple layers (including oxide-based and nitride-based layers) that are seamlessly integrated. This composite approach prevents SiN seam voids and electrical shorts while managing the manufacturing complexity through established multi-layer deposition techniques.
Data Source
AI summary
In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.