Source/Drain Spacer Structure for Low-Capacitance Nanosheet ICs
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Solution Overview
Problem
Conventional nano-sheet-based devices face challenges in balancing optimal current density and low fringe capacitance due to the lateral growth of source/drain features, which adversely impact device performance.
Innovation Solution
The formation of source/drain features with a narrower bottom portion and a wider top portion, along with the use of dielectric spacers to minimize contact resistance and control fringe capacitance, is implemented in the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If source/drain features are allowed to grow laterally to ensure adequate current density, then current density is improved, but fringe capacitance increases and adversely impacts device performance
Solution Approach 1:
The source/drain feature is divided into two distinct portions: a lower portion with a first width and an upper portion with a second width. This segmentation allows each portion to serve different functions - the lower portion provides current conduction path while the upper portion is controlled to minimize fringe capacitance effects.
Solution Approach 2:
Different portions of the source/drain feature are given different local properties. The lower portion has a larger cross-sectional area optimized for current carrying capacity, while the upper portion has a smaller cross-sectional area optimized for reducing fringe capacitance. This local differentiation resolves the contradiction between current density and fringe capacitance.
2Object-generated harmful factors
If source/drain features are made narrower to reduce fringe capacitance, then fringe capacitance is reduced, but contact resistance increases
Solution Approach 1:
The source/drain feature is segmented into lower and upper portions with different widths. The lower portion maintains adequate width to ensure low contact resistance at the contact interface, while the upper portion is narrowed to reduce fringe capacitance along the channel interface.
Solution Approach 2:
The source/drain feature exhibits different local dimensions at different positions. The lower portion near the contact has larger cross-sectional area for low resistance contact, while the upper portion near the channel has smaller cross-sectional area for reduced fringe capacitance, achieving both requirements simultaneously.
Data Source
AI summary
The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.