Source/Drain Spacer Height Layout for Fin Merge Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling critical dimensions (CDs) of source/drain regions to prevent yield loss, particularly in FinFET manufacturing, where undesired merging of epitaxial source/drain regions can lead to shorts and reduced device functionality.
Innovation Solution
The solution involves epitaxially growing n-type and p-type source/drain regions simultaneously while forming spacers of different heights in logic and SRAM device regions to control the merging of epitaxial source/drain regions, using a single epitaxial growth process to reduce process variations and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single epitaxial growth process is used to form source/drain regions, then process variations and manufacturing costs are reduced, but undesired merging of epitaxial source/drain regions occurs leading to shorts and yield loss
Solution Approach 1:
The device region is segmented into logic device regions and SRAM device regions, with different spacer heights formed in each segment. Logic device regions receive spacers at a first height that allows epitaxial source/drain regions to merge, while SRAM device regions receive spacers at a second height that prevents merging. This spatial segmentation resolves the contradiction by allowing the single epitaxial growth process to proceed while controlling merging behavior through localized spacer height differences.
Solution Approach 2:
Different spacer heights are formed at different locations within the device region. The spacer height is locally optimized for each device type: shorter spacers in logic device regions to enable merging and longer spacers in SRAM device regions to prevent merging. This local quality adjustment allows the single epitaxial growth process to achieve different outcomes in different areas, resolving the contradiction between process simplicity and dimensional control precision.
2Reliability
If spacer heights are increased to prevent merging of epitaxial source/drain regions, then yield loss is reduced, but critical dimension control becomes more difficult and device complexity increases
Solution Approach 1:
The device region is divided into logic device regions and SRAM device regions with different spacer height requirements. By segmenting the region and forming spacers at different heights only where needed, the solution prevents shorts in SRAM regions without unnecessarily increasing complexity across the entire device. The segmentation allows targeted application of different spacer heights to different device types.
Solution Approach 2:
The spacer height is locally adjusted based on device type: logic device regions use spacers at a first height while SRAM device regions use spacers at a second height. This local quality approach ensures that the increased spacer height for preventing merging is applied only where necessary (in SRAM regions), rather than uniformly across all devices, thereby reducing overall device complexity while maintaining reliability.
3Manufacturing precision
If multiple epitaxial growth processes are used to control merging, then critical dimension control improves, but process complexity and manufacturing costs increase
Solution Approach 1:
Spacer layers with different heights are formed in advance, before the epitaxial growth process, using selective etching techniques. This preliminary action of creating height-differentiated spacers allows a single subsequent epitaxial growth process to produce different outcomes in different regions. The preliminary structuring of spacers eliminates the need for multiple epitaxial growth processes while maintaining precise control over source/drain region merging behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively inhibits undesired merging of epitaxial source/drain regions, reducing yield loss and improving device functionality by controlling the critical dimensions of source/drain regions, thereby enhancing the integration density and performance of semiconductor devices.
Implementation Method 1
epitaxially growing a first source/drain region in the first recess and the second recess, a second source/drain region in the third recess, and a third source/drain region in the fourth recess
Data Source
AI summary
A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.