Source/Drain Spacer Layer to Prevent Phosphorus Segregation

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Solution Overview

Problem

Phosphorus segregation in multi-gate transistors, such as FinFETs and MBC transistors, leads to decreased active phosphorus concentration and increased source/drain resistance, deteriorating transistor performance due to phosphorus atoms clustering at nitride-containing dielectric surfaces.

Innovation Solution

A segregation preventing layer, composed of arsenic-containing materials, is deposited on the surfaces of inner and gate spacers to retard phosphorus segregation, maintaining a more even junction profile and reducing resistance by ensuring active phosphorus atoms remain available in the source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If phosphorus doping is applied to source/drain regions to reduce resistance, then electrical conductivity improves, but phosphorus atoms segregate at nitride-containing dielectric surfaces causing decreased active phosphorus concentration

Engineering Contradiction:

Improvetransistor performanceVSAvoidactive phosphorus concentration

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

An arsenic-containing segregation preventing layer is introduced as an intermediary between the phosphorus-doped source/drain regions and the nitride-containing dielectric surfaces. This intermediate layer has high affinity for phosphorus atoms, capturing them before they can segregate to the dielectric interface, thereby maintaining active phosphorus concentration in the source/drain regions while preserving the beneficial low-resistance effect of phosphorus doping.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The segregation preventing layer is deposited in advance before phosphorus doping or during subsequent processing steps to preemptively block phosphorus segregation. By establishing this protective barrier beforehand, the layer prevents phosphorus atoms from migrating to and clustering at the dielectric surface, thus maintaining electrical performance without requiring post-processing corrections.

Inventive Principle:

Principle #9Preliminary anti-action

2Reliability

If multi-gate transistor structures are used to improve gate control, then gate-channel coupling increases, but source/drain resistance increases due to phosphorus segregation

Engineering Contradiction:

Improvegate controlVSAvoidsource/drain resistance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The arsenic-containing segregation preventing layer serves as a mediator that decouples the relationship between multi-gate structures and phosphorus segregation. By intercepting phosphorus atoms before they reach dielectric surfaces, the layer eliminates the harmful resistance increase that would otherwise accompany multi-gate transistor operation, allowing full benefit from improved gate control without the penalty of elevated source/drain resistance.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The high affinity of arsenic for phosphorus, which initially causes phosphorus to concentrate at the segregation preventing layer interface, is converted into a benefit. This controlled concentration prevents uncontrolled segregation at dielectric surfaces, transforming what would be a harmful effect (phosphorus clustering) into a controlled mechanism that maintains active phosphorus in the source/drain regions and reduces resistance.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The segregation preventing layer enhances the drive current capability and improves device performance by increasing active phosphorus concentration and uniformity of the junction profile in the source/drain regions.

Implementation Method 1

A segregation preventing layer, composed of arsenic-containing materials, is deposited on the surfaces of inner and gate spacers

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

a segregation preventing layer, composed of arsenic-containing materials, is deposited on the surfaces of inner and gate spacers to retard phosphorus segregation

Methodology Applied

Scientific EffectDiffusion Barrier: Diffusion Barrier

Data Source

PatentUS20250220981A1Source/drain structure for semiconductor devices and manufacturing methods thereof

Publication Date: 2025.07.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers over a substrate, patterning the stack to form a fin-shape structure, forming a dummy gate stack over the fin-shape structure, recessing the fin-shape structure to form a source/drain trench, partially recessing the sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively depositing a segregation preventing layer on surfaces of the inner spacers, and forming an epitaxial feature in the source/drain trench. The surfaces of the inner spacers include a first surface exposed in the source/drain trench and a second surface facing an adjacent one of the channel layers. A portion of the segregation preventing layer is stacked between the inner spacers and the epitaxial feature.