Source/Drain Strain Engineering for Nano-Sheet Gate Control
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Solution Overview
Problem
Conventional nano-sheet-based devices face challenges in introducing sufficient and appropriate types of stresses into the source/drain features, which affects device performance.
Innovation Solution
The method involves engineering dislocations into the adjacent source/drain features by performing a pre-amorphous implantation process followed by annealing, which introduces controlled stress into the channel layers of nano-sheet-based devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nano-sheet-based devices are used, then gate control is improved and short-channel effects are reduced, but sufficient and appropriate stress cannot be introduced into the source/drain features
Solution Approach 1:
The patent applies preliminary action by performing pre-amorphous implantation before forming the source/drain features. This pre-treatment creates an amorphous region in the substrate that later facilitates controlled stress introduction during the epitaxial growth stage, resolving the contradiction by preparing the structure in advance to enable stress engineering.
Solution Approach 2:
The patent changes the physical and chemical parameters of the source/drain features through controlled epitaxial growth conditions, including temperature, pressure, and gas flow rates. These parameter changes enable precise control over the stress state (tensile or compressive) introduced into the source/drain regions, allowing sufficient and appropriate stress to be achieved while maintaining device reliability.
2Productivity
If geometry size is decreased, then production efficiency is increased and costs are lowered, but device performance and stress control become more difficult
Solution Approach 1:
The patent applies local quality by introducing different stress conditions into different regions of the device. Specifically, tensile stress is introduced into n-type source/drain features while compressive stress is introduced into p-type source/drain features through selective epitaxial growth conditions. This localized stress control maintains manufacturing precision even as geometry sizes decrease and production efficiency increases.
Solution Approach 2:
The patent utilizes parameter changes during epitaxial growth to control stress in scaled-down devices. By adjusting growth temperature, pressure, and gas composition, the patent achieves precise stress control in nanoscale source/drain features, maintaining manufacturing precision despite reduced geometry sizes and higher production volumes.
3Reliability
If stress is introduced into source/drain features, then charge carrier mobility is enhanced, but control over type, magnitude, and distribution of stress becomes challenging
Solution Approach 1:
The patent uses preliminary action through pre-amorphous implantation to create a prepared substrate structure that facilitates controlled stress introduction. This pre-treatment simplifies the overall stress control process by establishing a uniform amorphous region that responds predictably during subsequent epitaxial growth, reducing the complexity of achieving desired stress states while enhancing charge carrier mobility.
Solution Approach 2:
The patent implements feedback control through monitoring and adjusting epitaxial growth conditions to achieve target stress states. By controlling growth parameters and measuring the resulting stress distribution, the patent can iteratively optimize the stress magnitude and type, enabling precise control over stress characteristics while maintaining enhanced charge carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility, improving device performance by controlling the type, magnitude, and distribution of stress, thereby optimizing device speeds and reducing OFF-state current.
Implementation Method 1
implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer
Implementation Method 2
annealing the semiconductor substrate
Implementation Method 3
annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure
Data Source
AI summary
A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.