Source/Drain Strain Layer Structure for Nanostructure-FET Diffusion Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, issues arise with impurity diffusion and performance degradation due to reduced feature sizes, necessitating improved integration density and reduced diffusion of impurities in nanostructure field-effect transistors (nanostructure-FETs).
Innovation Solution
The implementation of strain layers made of semiconductor materials, such as germanium, over the sidewalls of channel regions in nanostructure-FETs to enhance tensile strain and reduce impurity diffusion, particularly for n-type devices, using epitaxial growth techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but impurity diffusion and performance degradation increase
Solution Approach 1:
A strain layer made of semiconductor material (e.g., silicon germanium) is introduced as an intermediary between the source/drain region and the channel region. This strain layer mediates the contradiction by providing mechanical strain to improve carrier mobility (enhancing performance) while being deposited using atomic layer deposition (ALD) which enables precise control at reduced feature sizes (supporting integration density). The strain layer acts as a buffer that prevents impurity diffusion into the channel while maintaining device performance.
Solution Approach 2:
The patent changes the material composition parameter by introducing a strain layer with different semiconductor material composition (e.g., silicon germanium with varying germanium content) between the source/drain and channel regions. This parameter change enables controlled strain to improve carrier mobility without compromising device reliability at reduced feature sizes. The graded composition of the strain layer allows gradual transition and prevents abrupt interface effects that could degrade performance.
2Productivity
If feature size is reduced to improve integration density, then manufacturing capacity increases, but impurity diffusion worsens
Solution Approach 1:
The strain layer serves as an intermediary barrier between the source/drain regions and the channel region. This intermediate layer physically blocks impurity diffusion from the source/drain regions into the channel region, preventing the harmful effect of impurity diffusion while allowing the device to be manufactured at reduced feature sizes for higher integration density.
Solution Approach 2:
The strain layer acts as a diffusion barrier that mediates between the source/drain regions and channel region, preventing impurity atoms from diffusing into the channel while maintaining the structural integrity and electrical performance of the device at reduced feature sizes.
3Reliability
If strain layers are added to reduce impurity diffusion and improve performance, then device reliability improves, but device complexity increases
Solution Approach 1:
The strain layer is applied locally only in specific regions where it is most needed - between the source/drain regions and channel region - rather than uniformly across the entire device. This localized application improves device performance and prevents impurity diffusion without unnecessarily increasing the complexity of the entire device structure. The strain layer is confined to where it provides maximum benefit.
Solution Approach 2:
The strain layer is formed using composite material approaches, such as silicon germanium alloys with graded composition, which combine different semiconductor materials to achieve the desired strain effect. This composite material approach improves device performance and reliability while the graded composition helps manage interface effects and reduces manufacturing complexity compared to abrupt interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strain layers improve the performance of n-type nanostructure-FETs by increasing tensile strain and reducing impurity diffusion, thereby enhancing the device's operational efficiency and reliability.
Implementation Method 1
The strain layer may comprise a semiconductor material that exerts a tensile stress on the channel region
Implementation Method 2
the channel region, and the strain layer are formed using epitaxial growth techniques
Data Source
AI summary
A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; a first source/drain region over the first insulating layer, wherein the first source/drain region includes a first semiconductor layer extending continuously over the sidewalls of the first nanostructures, wherein the first semiconductor layer is a first semiconductor material and a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is a second semiconductor material different from the first semiconductor material.