Source/Drain Strain Layer Structure for Nanostructure-FETs

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, issues arise with impurity diffusion and performance degradation due to reduced feature sizes, necessitating improved strain management and impurity control in semiconductor structures.

Innovation Solution

The implementation of continuous strain layers over the channel regions of nanostructure-FETs, composed of materials like germanium, enhances tensile strain and reduces impurity diffusion, particularly for n-type devices, using epitaxial growth techniques to form semiconductor layers that improve performance and reduce manufacturing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous strain layers composed of germanium are implemented over channel regions, then tensile strain is enhanced and device performance is improved, but impurity diffusion control becomes more critical and manufacturing complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidstrain layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain structure is segmented into multiple functional layers: a first semiconductor material layer forming the source/drain region, and a second semiconductor material layer forming the strain layer. This segmentation allows independent optimization of each layer's properties - the first layer provides electrical conduction while the second layer provides mechanical strain, resolving the contradiction between performance enhancement and manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The strain layer is applied locally only over the channel regions where tensile strain is needed for carrier mobility enhancement, rather than uniformly across the entire device. This localized application maximizes performance benefit while minimizing the overall structural complexity and material usage.

Inventive Principle:
Principle #3Local quality

2Productivity

If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but impurity diffusion and performance degradation increase

Engineering Contradiction:
Improveintegration densityVSAvoidperformance stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The strain layer acts as an intermediary structure between the source/drain regions and the channel. It mediates the mechanical stress transmission to enhance carrier mobility while simultaneously serving as a diffusion barrier that protects the channel from impurity contamination, thus maintaining performance stability at reduced feature sizes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The device employs composite material structures with distinct semiconductor material layers having different properties. The first layer (source/drain) and second layer (strain layer) are composed of different semiconductor materials optimized for their specific functions, creating a composite structure that addresses both integration density and performance stability requirements.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The strain layers enhance the performance of n-type nanostructure-FETs by increasing tensile strain and minimizing impurity diffusion, thereby improving device reliability and efficiency.

Implementation Method 1

using epitaxial growth techniques to form semiconductor layers that improve performance

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

The strain layers can reduce the diffusion of impurities into nanostructures during manufacturing

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20250344457A1Semiconductor source/drain regions and methods of forming the same
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250344457A1 patent drawing
  • US20250344457A1 patent drawing
  • US20250344457A1 patent drawing

AI summary

A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; a first source/drain region over the first insulating layer, wherein the first source/drain region includes a first semiconductor layer extending continuously over the sidewalls of the first nanostructures, wherein the first semiconductor layer is a first semiconductor material and a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is a second semiconductor material different from the first semiconductor material.