Semiconductor Source-Drain Stressor Layout for Mobility and Leakage

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Solution Overview

Problem

Existing semiconductor manufacturing technologies face challenges in optimizing carrier mobility and device performance across different threshold voltage devices, as stressors are typically formed in devices with lower threshold voltages but not in those with higher threshold voltages, leading to trade-offs between carrier mobility and leakage current.

Innovation Solution

The solution involves selectively forming stressors in source and drain regions of devices with lower threshold voltages during semiconductor device manufacturing, while omitting stressors in devices with higher threshold voltages, thereby enhancing carrier mobility in LVt devices and reducing leakage current in HVt devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stressors are formed in source and drain regions to enhance carrier mobility, then device performance is improved, but leakage current increases in devices with higher threshold voltages

Engineering Contradiction:
Improvedevice performanceVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by selectively forming stressors only in specific device regions (LVt devices) while omitting them from other regions (HVt devices). This is achieved through selective epitaxial growth in recesses that are selectively formed in certain source and drain regions, thereby applying stress locally where it benefits carrier mobility without introducing leakage current in regions where it would be harmful.

Inventive Principle:
Principle #3Local quality

2Reliability

If stressors are selectively formed only in devices with lower threshold voltages, then carrier mobility is enhanced in those devices, but devices with higher threshold voltages cannot benefit from improved device performance

Engineering Contradiction:
Improvecarrier mobilityVSAvoiddevice performance flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements local quality by creating spatially differentiated stressor formation. Through selective recess formation and selective epitaxial growth, stressors are introduced only in LVt device source and drain regions, allowing those specific devices to benefit from enhanced carrier mobility while HVt devices maintain their original characteristics without unwanted leakage current.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies segmentation by dividing the semiconductor device array into distinct groups based on threshold voltage characteristics. By forming recesses and subsequently growing stressors only in specific segmented regions (LVt devices), the patent enables differential treatment of device types, allowing optimization of carrier mobility in LVt devices while preserving the performance characteristics of HVt devices.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for improved carrier mobility and device performance in devices with lower threshold voltages, while maintaining low leakage current in devices with higher threshold voltages, thus offering flexibility in circuit design and meeting performance and leakage requirements in applications such as automotive and mobile devices.

Implementation Method 1

epitaxially growing a strained material in a first recess on a first side of a first gate structure and in a second recess on a second side of the first gate structure

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

forming stressors at opposite sides of the first gate structure, wherein forming the stressors comprise epitaxially growing a strained material

Methodology Applied
Scientific EffectMechanical stress: Stress Relaxation

Data Source

PatentUS12342610B2Method of manufacturing semiconductor device
Publication Date: 2025.06.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12342610B2 patent drawing
  • US12342610B2 patent drawing
  • US12342610B2 patent drawing

AI summary

A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.