Source-Drain Superlattice Contacts for Lower Semiconductor Resistance

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving enhanced charge carrier mobility and reduced contact resistance, which affect performance and efficiency.

Innovation Solution

The use of dopant diffusion blocking superlattices, such as Si/O superlattices, to divide source and drain regions, combined with oxygen insertion layers near the metal-semiconductor interface, to trap dopants and reduce Schottky barrier height and contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If dopant concentration in source and drain regions is increased to reduce contact resistance, then contact resistance decreases, but dopant diffusion into the channel region increases causing performance degradation

Engineering Contradiction:
Improvecontact resistanceVSAvoiddopant diffusion
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The source and drain regions are segmented into multiple zones with different dopant concentrations by inserting superlattice barrier layers. The superlattice divides the doped region such that high dopant concentration can be maintained near the contact without allowing diffusion into the channel, creating distinct dopant concentration zones that resolve the contradiction between low contact resistance and low dopant diffusion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The superlattice barrier layer acts as an intermediary between the heavily doped source/drain contact region and the channel region. This intermediate structure prevents direct dopant diffusion while allowing the high dopant concentration needed for low contact resistance to exist in the upper region, thus mediating between the conflicting requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If strained material layers are used to enhance charge carrier mobility, then device speed and performance improve, but manufacturing complexity increases

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidmanufacturing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent modifies the crystal structure parameters of the semiconductor material by introducing strained material layers with different lattice constants. This changes the band structure and effective mass of charge carriers, thereby enhancing mobility without requiring fundamental changes to the manufacturing process, thus improving speed while managing manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances charge carrier mobility and reduces contact resistance, leading to improved device performance and efficiency by lowering the effective mass of charge carriers and stabilizing the interface with metal contacts.

Implementation Method 1

at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions

Methodology Applied
Scientific EffectAdsorption: Adsorption

Implementation Method 2

applying heat to move upward oxygen atoms from the at least one oxygen monolayer to react with the at least one metal layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentEP3871266B1Method for making a semiconductor device having reduced contact resistance
Publication Date: 2025.10.22 ATOMERA INC
  • EP3871266B1 patent drawingFigure 1
  • EP3871266B1 patent drawingFigure 2
  • EP3871266B1 patent drawingFigure 3

AI summary

A method for making a semiconductor device may include forming spaced apart source and drain regions (1021, 103') in a semiconductor layer (101') with a channel region (130') extending therebetween. At least one of the source and drain regions may be divided into a lower region (104', 106') and an upper region (105', 107') by a dopant diffusion blocking superlattice (125') with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate (108') on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.