Source/Drain Contact Structure for TDDB Isolation Control
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Solution Overview
Problem
As semiconductor integrated circuits scale down beyond 32 nm, poor isolation between nearby source/drain contacts leads to time-dependent dielectric breakdown (TDDB) failures, necessitating improved methods for increasing isolation between these contacts.
Innovation Solution
The use of isotropic etching of the dielectric layer over source/drain electrodes, allowing for separate processing of dense and isolated transistor regions to achieve better control of the etching profile and maintain maximum distance between adjacent source/drain contacts, thereby enhancing TDDB performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used for source/drain contacts, then manufacturing simplicity is maintained, but isolation between adjacent contacts deteriorates leading to TDDB failures
Solution Approach 1:
The patent divides the etching process into two distinct segments: a first etching process that forms initial contact holes, and a second etching process that forms final contact holes with improved isolation. This segmentation allows each process to be optimized independently, with the second process specifically tailored to maintain vertical sidewalls and increase distance between adjacent contacts, thereby resolving the TDDB issue without requiring complete process redesign
Solution Approach 2:
The first etching process serves as a preliminary action that prepares the structure for the final etching step. By first forming contact holes and then performing a second etching to create the final contact structure, the process ensures proper isolation is established before metal deposition, preventing TDDB failures while maintaining manufacturing feasibility
2Reliability
If distance between source/drain contacts is increased to improve isolation, then TDDB performance improves, but contact area decreases affecting electrical performance
Solution Approach 1:
The patent applies different etching conditions to different regions of the substrate. In dense transistor regions, the etching process is optimized to maintain adequate isolation, while in isolated transistor regions, the process allows for larger contact areas. This local optimization ensures that each region receives the appropriate contact dimensions for its specific density requirements, maintaining both isolation quality and electrical performance
Solution Approach 2:
The etching process parameters are made dynamic rather than fixed, allowing adjustment based on local transistor density. The process can adapt between aggressive etching for isolated regions (maintaining large contact area) and controlled etching for dense regions (ensuring proper isolation), thereby resolving the contradiction between contact area and isolation quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the distance between adjacent source/drain contacts, improving the semiconductor device's TDDB performance by maintaining vertical or substantially vertical sidewalls during the etching process, thus reducing the risk of dielectric breakdown.
Implementation Method 1
performing a second etching process to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes, wherein the second etching process includes isotropic etching
Data Source
AI summary
A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.