3D Source/Drain Pattern Structure for Semiconductor Integration
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Solution Overview
Problem
Semiconductor devices face challenges in achieving improved electrical characteristics due to complex integration and high-speed requirements, with existing designs struggling to optimize source/drain patterns for enhanced performance.
Innovation Solution
The semiconductor device design incorporates a plurality of active patterns on a substrate with a device isolation layer and a source/drain pattern comprising multiple parts, where the source/drain pattern extends along the upper portion of the active patterns, with specific depth and valley configurations to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source/drain pattern is extended along the upper portion of active patterns with multiple parts and valleys, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The source/drain pattern is divided into multiple discrete parts (first part, second part, third part) separated by valleys, allowing each segment to be independently formed and optimized on different active patterns. This segmentation enables improved electrical characteristics through selective doping and contact formation while managing complexity through modular fabrication steps.
Solution Approach 2:
The source/drain pattern extends vertically along the upper portion of active patterns, utilizing the third dimension (height/depth) rather than only horizontal plane. The pattern includes portions at different elevations, with some parts extending higher than others, creating a three-dimensional structure that improves electrical performance by increasing contact area and reducing resistance.
2Manufacturing precision
If the source/drain pattern parts are merged together, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Multiple source/drain parts are merged into a unified continuous pattern that spans across multiple active patterns. The first, second, and third parts are connected through the valley regions, forming an integrated structure that simplifies manufacturing by reducing the number of separate formation steps while maintaining precise alignment through the merging process.
Data Source
AI summary
A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.