Source/Drain Via Etch Stop Structure for Leakage Control
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Solution Overview
Problem
The challenge in integrated circuit (IC) manufacturing is to prevent over-etching during the formation of source/drain vias and contacts, which can lead to leakage current and reduced device performance, especially as technology nodes shrink.
Innovation Solution
The implementation of a middle contact etch stop layer (MCESL) and plasma treatment to form oxidation regions in dielectric materials, combined with self-aligned contact processes, ensures precise etching and reduces the risk of over-etching by slowing down the etching process, thereby preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for source/drain via formation, then etching speed is maintained, but over-etching occurs leading to leakage current and reduced device performance
Solution Approach 1:
The etching process is segmented into multiple distinct stages: a first etching process to form initial via openings through the interlayer dielectric layer, and a second etching process to complete the via openings through the contact etch stop layer. This segmentation allows each etching stage to be optimized independently, preventing over-etching while maintaining etching speed.
Solution Approach 2:
A contact etch stop layer is introduced as an intermediary layer between the interlayer dielectric layer and the underlying structures. This intermediate layer serves as a controlled barrier that prevents the etching process from penetrating too deeply, thereby preventing over-etching and the associated leakage current issues while allowing the etching to proceed at appropriate speeds.
2Productivity
If geometry size is reduced to increase functional density, then production efficiency increases and costs decrease, but over-etching becomes more severe
Solution Approach 1:
The contact etch stop layer acts as an intermediary that provides precise etching control, which is especially critical when geometry sizes are reduced. This intermediate layer ensures that etching can be accurately controlled at smaller dimensions, preventing over-etching that would be more severe at reduced geometry sizes while maintaining the productivity gains from scaling.
Solution Approach 2:
The contact etch stop layer is formed in advance before the etching process begins. This preliminary action prepares a controlled barrier that will precisely limit the etching depth, enabling accurate etching control as geometry sizes are reduced to increase functional density and production efficiency.
3Productivity
If etching speed is increased to maintain productivity, then production efficiency is maintained, but over-etching risk increases
Solution Approach 1:
The etching process is divided into segmented stages with the first etching process forming initial via openings and the second etching process completing the openings through the contact etch stop layer. This segmentation allows high etching speed to be maintained in the first stage while the second stage provides precise control to prevent over-etching, thus maintaining both productivity and etching precision.
Solution Approach 2:
The contact etch stop layer serves as an intermediary that enables high etching speeds without increasing over-etching risk. The etching process can proceed rapidly through the interlayer dielectric layer, and the contact etch stop layer then acts as a controlled barrier that prevents over-etching, maintaining etching precision even at high speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents over-etching, reduces leakage current, and enhances the electrical performance of ICs by maintaining precise control over etching processes, even at smaller technology nodes.
Implementation Method 1
plasma treatment to form oxidation regions in dielectric materials
Data Source
AI summary
A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.