FET Source/Drain Via Metal Homogeneity for Lower Contact Resistance
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Solution Overview
Problem
The challenge in semiconductor integrated circuit manufacturing lies in forming contacts and vias to the gate, source, and drain electrodes of field-effect transistors, particularly due to high contact resistance caused by lattice constant mismatch and electron scattering, which is exacerbated by the use of different metals and challenging bottom-up processes that lead to voids and degraded adhesion.
Innovation Solution
Selecting the same metal for both contact and via metals, such as tungsten, ruthenium, cobalt, or copper, and employing a post-deposition annealing process to simplify processing and reduce grain boundary resistance, thereby eliminating the need for complex bottom-up or sidewall metallic material removal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different metals are used for contact and via structures, then electrical connectivity is improved, but contact resistance increases due to lattice constant mismatch and electron scattering
Solution Approach 1:
The patent applies homogeneity by using the same metal material for both contact structures and via structures. This eliminates the interface between different metals, thereby removing lattice constant mismatch and electron scattering effects that occur at metal interfaces. The uniform material composition throughout the conductive path reduces contact resistance and improves electrical connectivity.
2Ease of manufacture
If bottom-up processes are used to form contact structures, then manufacturing complexity is reduced, but voids form and adhesion degrades
Solution Approach 1:
The patent applies preliminary action by performing annealing treatment after depositing the metallic material but before forming the final contact structure. This post-deposition annealing process pre-treats the metal layer to improve grain structure and reduce defects, preventing void formation and adhesion degradation in subsequent processing steps. The annealing prepares the material in advance to avoid the problems associated with bottom-up formation processes.
3Manufacturing precision
If complex bottom-up or sidewall metallic material removal processes are used, then contact precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies the extraction principle by removing the complex bottom-up formation process and sidewall metallic material removal steps entirely. Instead, a simpler deposition and annealing process is used that directly forms high-quality contact structures without requiring these intermediate complex steps. The harmful complex processes are extracted and replaced with a more efficient approach.
Solution Approach 2:
The patent applies parameter changes by modifying the thermal processing parameters through post-deposition annealing. By controlling temperature, time, and atmosphere parameters during annealing, the metal layer achieves optimal grain structure and adhesion properties. This parameter optimization allows simpler processing while maintaining or improving contact formation precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and enhances device performance by ensuring uniform material composition across contacts and vias, improving electrical connectivity and simplifying the manufacturing process.
Implementation Method 1
employing a post-deposition annealing process to simplify processing and reduce grain boundary resistance
Data Source
AI summary
A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.