Source/Drain Void Structure for Lower Parasitic Capacitance

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Solution Overview

Problem

The continuous scaling down of semiconductor devices to meet demands for higher performance and lower power consumption is hindered by increased parasitic capacitance in source/drain structures, which limits device performance.

Innovation Solution

Incorporating a void into the source/drain structure of semiconductor devices, specifically within a nanostructure transistor, reduces parasitic capacitance by adjusting the ratios of horizontal and vertical dimensions of the void to the source/drain structure, thereby enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the dimensions of semiconductor devices are scaled down to meet demands for higher performance and lower power consumption, then device performance and power efficiency are improved, but parasitic capacitance in source/drain structures increases

Engineering Contradiction:

Improvepower consumptionVSAvoidparasitic capacitance

Core Design Contradiction:

PowerVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the problematic region (source/drain structure) and removes material to create a void, separating the conductive function from the capacitive coupling problem. The void is positioned between the gate and the source/drain structure to eliminate parasitic capacitance while preserving electrical connectivity through the void's strategic placement.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a void (porous space) within the source/drain structure to reduce parasitic capacitance. This porous approach allows the structure to maintain its mechanical and electrical functions while eliminating the harmful capacitive coupling between the gate and source/drain regions.

Inventive Principle:

Principle #31Porous materials

2Object-generated harmful factors

If a void is introduced into the source/drain structure to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidstructure complexity

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The source/drain structure is segmented into multiple regions with different properties: a first portion with higher doped concentration and a second portion with lower doped concentration. The void is strategically positioned between these segments, allowing each segment to serve specific functions while collectively reducing parasitic capacitance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the source/drain structure are assigned different dopant concentrations to optimize local electrical properties. The high-doped region provides low resistance contact, while the low-doped region reduces parasitic capacitance, creating local quality variations that solve the overall problem.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250234611A1Source/drain structures with void for semiconductor devices

Publication Date: 2025.07.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a semiconductor device having a source/drain (S/D) structure with a void. The semiconductor device includes a stack of semiconductor layers on a substrate, a gate structure surrounding the stack of semiconductor layers, and a S/D structure on the substrate and in contact with the stack of semiconductor layers. The S/D structure includes a void below a top surface of the S/D structure.