Source/Drain Contact Openings With Two-Step Width Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in controlling the width of contact openings to source/drain regions, leading to potential shorting of adjacent regions and reducing manufacturing yield.
Innovation Solution
The formation of contact openings is initiated at a smaller width and then expanded to a larger width in a separate etching process, with a protective layer used to safeguard surrounding features during the creation of metal-semiconductor alloy regions on the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If contact openings are formed directly at the required width, then manufacturing process is simpler, but control over contact opening width is poor leading to shorting of adjacent regions
Solution Approach 1:
The contact opening formation process is divided into two separate etching steps: first forming openings at a smaller initial width, then expanding them to the final required width. This segmentation allows precise control over the final contact opening dimensions while preventing shorting of adjacent regions.
Solution Approach 2:
A protective layer is deposited on the gate mask before forming contact openings. This preliminary protective action prevents the gate mask from being damaged during subsequent etching and cleaning processes, particularly during metal-semiconductor alloy region formation.
2Reliability
If contact openings are formed with larger width to ensure proper contact, then contact reliability is improved, but adjacent source/drain regions may short
Solution Approach 1:
The two-step etching process first creates openings at a controlled smaller width, then selectively expands them. This ensures contact openings are large enough for reliable contact while maintaining sufficient spacing between adjacent contacts to prevent shorting.
Solution Approach 2:
The protective layer is selectively applied to the gate mask area, providing localized protection during the metal-semiconductor alloy formation process. This allows the contact openings to be formed with precise dimensions without compromising adjacent regions.
3Ease of manufacture
If gate mask is exposed during metal-semiconductor alloy formation, then alloy region formation is simpler, but gate mask is damaged requiring rework
Solution Approach 1:
The protective layer is deposited on the gate mask before any etching or alloy formation processes. This preliminary protection allows the metal-semiconductor alloy regions to be formed directly on exposed source/drain regions without worrying about gate mask damage, eliminating the need for protective removal steps.
Solution Approach 2:
The protective layer acts as an intermediary between the gate mask and the aggressive etchants/cleaning solutions used during alloy formation. It shields the gate mask from damage while allowing the alloy formation process to proceed on the source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the control over contact opening widths, preventing shorting and enhancing manufacturing yield by protecting surrounding features during the formation of metal-semiconductor alloy regions.
Implementation Method 1
the protective layer covering the gate mask during the cleaning process
Implementation Method 2
annealing the metal to form a metal-semiconductor alloy region on the source/drain region
Implementation Method 3
etching an opening through the protective layer, the opening exposing the source/drain region
Data Source
AI summary
In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.