Source Driver Channel Circuit for Display Panel Frequency
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Solution Overview
Problem
The operation frequency of display panels is limited by the slew rate of signal input terminals in channel circuits of source drivers, due to parasitic capacitances in metal lines and input buffer circuits, which restricts the line driving period as frequency increases.
Innovation Solution
Incorporating multiple digital-to-analog converters and switches in each channel circuit of the source driver, allowing for switching operations among signal paths to facilitate increased operation frequency by charging or discharging corresponding paths and providing driving signals to data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation frequency of the display panel is increased, then the productivity is improved, but the signal slew rate becomes insufficient due to parasitic capacitances
Solution Approach 1:
The patent divides the single DAC output into multiple parallel output paths, each with its own buffer circuit. This segmentation allows simultaneous charging of multiple signal paths, effectively multiplying the signal transition capacity and enabling higher operation frequencies without sacrificing slew rate.
Solution Approach 2:
The patent implements preliminary charging of signal paths by maintaining multiple buffer circuits in ready states. Before a signal transition is needed, the corresponding buffer circuit and its associated signal path are already charged and prepared, eliminating delays that would occur with sequential charging in traditional single-path architectures.
2Loss of time
If the operation frequency is increased, then the line driving period is shortened, but the parasitic capacitances prevent adequate signal transition
Solution Approach 1:
By segmenting the signal path into multiple parallel channels, each channel handles a portion of the total signal transition load. This reduces the effective capacitance that each individual buffer circuit must charge within the line driving period, allowing faster transitions even at reduced time intervals.
Solution Approach 2:
The patent maintains continuous readiness of multiple buffer circuits through parallel architecture. While one buffer is actively driving a signal, others remain charged and ready, ensuring uninterrupted signal transitions. This continuity eliminates idle time between signal paths and maximizes the utilization of the available line driving period.
3Productivity
If multiple digital-to-analog converters are added to increase operation frequency, then the productivity improves, but the device complexity increases
Solution Approach 1:
The patent merges multiple buffer circuits into a shared output structure that drives common data lines. While multiple DACs and buffer circuits are present, their outputs are combined to drive the same display panel data lines, reducing the need for completely separate output stages and minimizing overall system complexity.
Solution Approach 2:
Each buffer circuit in the parallel architecture is designed with universal functionality to drive data lines. The buffer circuits can be selectively activated based on which signal path requires driving, making the system multi-functional while using standardized circuit blocks. This universality reduces design complexity compared to having completely dedicated circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the operation frequency of display panels by enabling efficient signal transmission and reducing the impact of parasitic capacitances, thereby improving the line driving period and overall panel performance.
Implementation Method 1
The DAC 11 may convert digital pixel data D11 into an analog signal and output the analog signal to the output buffer circuit 12
Implementation Method 2
The metal line 13 has a parasitic capacitance (a trace capacitance) C13, and the input terminal of the output buffer circuit 12 has a parasitic capacitance (an input capacitance) C12
Data Source
AI summary
A source driver, including a plurality of channel circuits, each of the plurality of channel circuits including a first digital-to-analog converter (DAC), a second DAC, a first switch, a second switch and an output buffer circuit, is provided. The output terminal of the output buffer circuit is configured to be coupled to a data line of a display panel. An output terminal of the first DAC is coupled to a first input terminal among the input terminals of the output buffer circuit. An output terminal of the second DAC is coupled to a second input terminal among the input terminals of the output buffer circuit. The first switch is disposed along a first signal path between the output terminal of the first DAC and the output terminal of the output buffer circuit. The second switch is disposed along a second signal path between the output terminal of the second DAC and the output terminal of the output buffer circuit.