Source Driver Chip OR/AND Logic for Electrostatic Interference
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Solution Overview
Problem
Source driver chips in display devices are susceptible to electrostatic interference, leading to abnormal pictures and failed testing results, particularly when electrostatic interference reaches class C intensity.
Innovation Solution
The source driver chip incorporates an OR logic arithmetic unit, a clock buffer, a shift register, and an AND logic arithmetic unit to generate and manipulate signals, performing OR and AND logic operations to reduce or eliminate electrostatic interference, enhancing the chip's anti-electrostatic interference ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source driver chip uses conventional logic circuits for signal processing, then the chip structure is simple and easy to manufacture, but the chip is highly susceptible to electrostatic interference causing abnormal pictures and testing failures
Solution Approach 1:
The patent introduces an intermediary signal processing mechanism using OR and AND logic units between the line latch signal and the clock buffer. The OR logic unit combines the line latch signal with a first output data delay control enabling signal, and the AND logic unit combines the result with a second output data delay control enabling signal. This intermediary logic structure filters and processes signals to prevent electrostatic interference from directly affecting the clock buffer, thereby improving reliability while adding controlled complexity to the circuit architecture.
2Reliability
If the source driver chip adds protective logic units to reduce electrostatic interference, then the anti-electrostatic interference ability is improved, but the device complexity and signal processing steps increase
Solution Approach 1:
The patent changes the logical parameters of signal processing by introducing delayed control enabling signals (first and second output data delay control enabling signals) that are generated based on the line latch signal timing. These parameter changes in signal generation timing and logic operations allow the circuit to maintain simplicity while adding protective functionality. The OR and AND logic units modify the signal parameters dynamically to prevent electrostatic interference without requiring complex additional circuitry.
3Ease of manufacture
If the source driver chip uses standard logic circuits without additional protective mechanisms, then the manufacturing process is simple, but electrostatic interference causes abnormal pictures and requires reboot for recovery
Solution Approach 1:
The patent implements preliminary action by generating the first and second output data delay control enabling signals in advance based on the line latch signal timing. These control signals are prepared before electrostatic interference occurs, allowing the OR and AND logic units to be pre-configured to filter out interference. This preliminary signal generation and configuration enables the chip to maintain normal operation under electrostatic interference conditions while keeping the manufacturing process relatively simple by using standard logic circuit techniques.
Data Source
AI summary
A source driver chip and a display device are disclosed. The source driver chip includes an OR logic arithmetic unit, a clock buffer, a shift register, and an AND logic arithmetic unit. An OR logic operation is performed on a line latch signal and a first output data delay control enabling signal to obtain a second output data delay control enabling signal, and an AND logic operation is performed on an initial line latch sub-signals and the second output data delay control enabling signal, such that electrostatic interference of the line latch signal can be reduced.