Source Driver DMS Blocks for Precise Data Signal Timing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High operating frequencies and large numbers of pixels in display devices make it difficult to control the timing of data output precisely due to excessive delays in transferring carry signals between shift registers, leading to inadequate image information being output to the display panel.
Innovation Solution
A source driver circuit with digital multi-spread (DMS) blocks that generate timing control signals using clocks delayed by a reference period, each block comprising an enable signal generator and a delay unit, allowing for precise timing control of data signals without relying on carry signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If carry signals are used to generate timing control signals in shift registers, then the circuit structure is simple, but the timing precision deteriorates due to excessive delay at high frequencies and large pixel counts
Solution Approach 1:
The invention divides the timing control function into multiple independent DMS blocks, each generating timing signals for specific pixel groups. This segmentation eliminates the need for sequential carry signal propagation across the entire display, reducing cumulative delay while maintaining circuit simplicity through modular design.
Solution Approach 2:
The invention introduces DMS blocks as intermediary timing control units between the clock signal source and the pixel output stages. These blocks generate localized timing control signals using direct clock inputs, acting as mediators that eliminate the harmful carry signal delay chain while preserving synchronized operation across the display.
2Ease of manufacture
If carry signals are transferred between shift registers, then the circuit implementation is straightforward, but the pixel charging time is insufficient leading to improper image output
Solution Approach 1:
By segmenting the display into multiple DMS blocks that operate independently with direct clock inputs, each block can generate timing signals optimized for its specific pixel group. This eliminates the sequential delay caused by carry signal propagation, ensuring each pixel group receives timing signals early enough for proper charging while maintaining ease of implementation through standardized block design.
Solution Approach 2:
The DMS blocks generate timing control signals in advance for each pixel group using direct clock inputs, before the actual data signal needs to be output. This preliminary generation of timing signals ensures sufficient pixel charging time is available, preventing improper image output while keeping the circuit implementation straightforward through pre-synchronized block operation.
3Productivity
If the operating frequency is increased to improve display performance, then the scanning rate improves, but the timing control precision deteriorates due to carry signal delay
Solution Approach 1:
The invention segments the timing control into multiple DMS blocks that can operate independently at high frequencies. Each block receives clock signals directly and generates timing control signals for its associated pixel group without waiting for carry signals from previous blocks, enabling high scanning rates while maintaining precise timing control within each segment.
Solution Approach 2:
The DMS blocks preliminarily generate timing control signals for each pixel group based on direct clock inputs, ensuring that timing synchronization is established before high-speed scanning begins. This preliminary timing setup allows the system to operate at high scanning rates without sacrificing timing precision, as each block is already synchronized and ready to operate at the target frequency.
Data Source
AI summary
A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.