Source Driver Blocks Dummy Line Voltage Using Arrival Time Detection
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Solution Overview
Problem
Display devices face excessive power consumption due to the presence of data dummy lines on the data driving unit that are not connected to the data lines on the display panel, as they still receive data voltages from the data driving unit.
Innovation Solution
Incorporating a timing controller that outputs a test signal during a reset section, allowing the source driving chip to block data voltage output to dummy lines with an arrival time period less than or equal to a reference time period, thereby reducing unnecessary power consumption by preventing voltage application to these lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data dummy lines are arranged on the data driving unit, then the data driving unit can be configured with more data driving lines, but excess power is consumed because data voltages are output to the dummy lines that are not connected to data lines
Solution Approach 1:
The source driving chip performs preliminary detection during the reset section by monitoring the arrival time period of test voltages to identify dummy lines before the normal data driving operation. This preliminary action allows the chip to block data voltage output to dummy lines in subsequent frames, preventing unnecessary power consumption while maintaining the ability to drive real data lines.
2Ease of operation
If data voltages are output to all data driving lines including dummy lines, then the data driving unit operates simply, but unnecessary power consumption occurs
Solution Approach 1:
The source driving chip uses feedback from the test voltage arrival time period detection to control its data voltage output behavior. By comparing the measured arrival time period against a reference value, the chip receives feedback information about whether a line is a dummy line, and adjusts its output accordingly to block data voltages to dummy lines while maintaining operation on valid data lines.
Data Source
AI summary
A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.