Source Driver IC Equalizer Control for Signal Glitch Prevention

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Solution Overview

Problem

The existing Embedded Panel Interface (EPI) protocol for liquid crystal display devices experiences signal distortion and waveform glitches due to external noise and impedance mismatching when connected in a multidrop manner, leading to malfunction of source driver ICs and abnormal noise on the screen.

Innovation Solution

Incorporating an equalizer control circuit in the source driver ICs that initializes the equalizer when the clock recovery circuit is in an unlock state and the equalization setting value is changed, preventing signal boosting and maintaining a stable clock recovery loop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the equalizer boosts the data signal to compensate for signal loss, then the signal strength is improved, but signal distortion and waveform glitches occur due to external noise and impedance mismatching

Engineering Contradiction:
Improvesignal strengthVSAvoidsignal distortion and waveform glitches
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the equalization setting value parameter to control the equalizer's boosting level. By dynamically adjusting this parameter based on lock status, the system optimizes signal strength while preventing over-boosting that causes distortion and waveform glitches.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the clock recovery circuit's lock status is monitored and fed back to the equalizer control circuit. When the lock status is unstable or lost, the feedback triggers initialization of the equalizer, preventing signal distortion and waveform glitches from occurring.

Inventive Principle:
Principle #23Feedback

2Reliability

If the equalizer continuously boosts the signal with high EQ setting value, then signal reception is improved, but the clock recovery circuit cannot lock due to waveform distortion

Engineering Contradiction:
Improvesignal receptionVSAvoidclock recovery lock status
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent makes the equalizer's operation dynamic by changing its behavior based on clock recovery lock status. When locked, the equalizer operates with higher boosting; when unlocked or transitioning, it initializes to a neutral state, allowing the system to adapt to changing signal conditions and maintain both reception quality and clock recovery accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies preliminary anti-action by initializing the equalizer before clock recovery attempts when the lock status is unstable. This prevents waveform distortion from occurring in the first place, ensuring that the clock recovery circuit can successfully lock without interference from distorted waveforms.

Inventive Principle:
Principle #9Preliminary anti-action

3Stability of the object's composition

If the equalizer is initialized frequently to prevent distortion, then waveform stability is improved, but the signal strength may become insufficient for reliable reception

Engineering Contradiction:
Improvewaveform stabilityVSAvoidsignal reception reliability
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent uses feedback from the clock recovery circuit's lock status to control equalizer initialization. The equalizer is initialized only when the lock status is unstable or lost, not continuously. This selective feedback-based approach maintains waveform stability while preserving signal strength for reliable reception during normal operation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9589524B2Display device and method for driving the same
Publication Date: 2017.03.07 LG DISPLAY CO LTD
  • US9589524B2 patent drawing
  • US9589524B2 patent drawing
  • US9589524B2 patent drawing

AI summary

A display device includes a source driver integrated circuit (IC) including an equalizer for boosting a data signal received through a pair of signal lines depending on an equalization (EQ) setting value and a clock recovery circuit recovering a clock of the data signal, and a timing controller, which is connected to the source driver IC through the signal line pair and transmits the data signal to the source driver IC. The source driver IC samples the data signal in conformity with a timing of an internal clock output when the clock recovery circuit is in a lock state. The source driver IC further includes an equalizer control circuit for initializing the equalizer when the clock recovery circuit is in an unlock state and the EQ setting value is changed.