Source Driver IC Layout Overlap Reduces Chip Footprint
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Solution Overview
Problem
Conventional source driving integrated circuits for display devices require additional space for fan-out areas, leading to increased chip size due to the separation of source driver, ESD circuit, and fan-out areas, which limits the reduction of the short side length and overall chip size.
Innovation Solution
The integration of a fan-out area that electrically connects source driver units to ESD units within the ESD circuit area in a horizontal structure of a semiconductor integrated circuit, allowing the fan-out area to overlap the ESD circuit area, thereby eliminating the need for additional space and reducing the short side length of the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source driver area, ESD circuit area, and fan-out area are separated in a horizontal structure, then each functional area can be independently designed and manufactured, but the chip size increases due to the additional space required for the fan-out area
Solution Approach 1:
The patent merges the fan-out area with the ESD circuit area by positioning the fan-out area to overlap with the ESD circuit area in the horizontal structure. This integration eliminates the need for separate dedicated space for fan-out connections, thereby reducing the overall chip size while maintaining independent design capabilities through vertical layering
Solution Approach 2:
The patent transitions from a purely horizontal separation of functional areas to a three-dimensional layout where the fan-out area overlaps vertically with the ESD circuit area. This dimensional change allows conduction lines to route through overlapping regions, effectively utilizing vertical space to reduce horizontal chip footprint
2Ease of operation
If the fan-out area is separated from the ESD circuit area, then electrical connections can be clearly organized, but the short side length of the chip cannot be reduced
Solution Approach 1:
The patent uses vertical layering to route conduction lines through the overlapping region of the fan-out area and ESD circuit area. This three-dimensional approach allows electrical connections to be organized clearly through vertical separation of signal layers while maintaining a compact horizontal footprint that reduces the short side length
3Reliability
If additional space is allocated for the fan-out area, then reliable electrical connections between source driver units and ESD units are ensured, but the overall chip size increases
Solution Approach 1:
The patent combines the fan-out area with the ESD circuit area in the horizontal layout, using vertical layering to maintain reliable electrical connections. The conduction lines are routed through the overlapping region with proper layer stacking and via connections, ensuring connection reliability while eliminating wasted horizontal space
Solution Approach 2:
The patent employs three-dimensional routing where conduction lines traverse vertical layers within the overlapping fan-out and ESD circuit areas. This approach maintains reliable electrical connections through proper layer design and via structures while compressing the horizontal chip footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the length of the short side of the source driving integrated circuit, resulting in a smaller chip size without the need for additional space, while maintaining efficient electrical connections between source driver and ESD units.
Implementation Method 1
an electrostatic discharge (ESD) circuit area including a plurality of ESD units
Data Source
AI summary
A source driving integrated circuit is provided. The source driving integrated circuit includes a source driver area, an electrostatic discharge (ESD) circuit area and a fan-out area. The source driver area includes a plurality of source driver units. The ESD circuit area includes a plurality of ESD units. The fan-out area includes conduction lines for electrically connecting respective ones of the source driver units of the source driver area to ones of the plurality of the ESD units of the ESD circuit area. In a horizontal structure of a semiconductor integrated circuit, the fan-out area at least partially overlaps the ESD circuit area.