Source Driver Multiplexing for Dot Inversion Modes
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Solution Overview
Problem
Conventional source drivers face challenges in reducing circuit complexity and chip size while supporting multiple dot inversion modes, leading to increased complexity and size with the addition of multiplexers.
Innovation Solution
A source driver design that includes a first latch circuit for parallel arrangement of data blocks using non-overlapping latch control signals, a second latch circuit for simultaneous latching, and a control circuit for generating selection signals based on polarity and inversion mode control signals, along with a digital-to-analog conversion circuit, multiplexing circuit, and output buffer to manage data transmission efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional multiplexers are added to support multiple dot inversion modes, then the adaptability of the source driver is improved, but the device complexity and chip size increase
Solution Approach 1:
The latch control circuit is designed to generate multiple types of latch control signals (first type and second type) using the same circuit structure. By controlling the selection signal input, the circuit can switch between different signal generation modes, enabling the source driver to support multiple dot inversion modes (one-DOT, n-DOT, and non-inversion modes) without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The latch control circuit dynamically changes its output behavior based on the selection signal. When the selection signal is at a first level, it generates first type latch control signals; when at a second level, it generates second type latch control signals. This dynamic switching capability allows the same hardware to adapt to different operating modes, reducing the need for additional fixed circuitry.
2Adaptability or versatility
If additional multiplexers are added to support multiple dot inversion modes, then the adaptability of the source driver is improved, but the chip size increases
Solution Approach 1:
The latch control circuit serves multiple functions by generating different types of latch control signals based on the selection signal input. This multi-functional design eliminates the need for separate dedicated circuits for each dot inversion mode, thereby reducing the overall chip area required to support multiple modes.
Solution Approach 2:
The circuit merges the functionality of multiple signal generation paths into a single latch control circuit. By combining the capabilities of generating both first type and second type latch control signals within one circuit, the design reduces the total number of components and the associated chip area.
3Productivity
If data blocks are arranged in parallel using non-overlapping latch control signals, then the data transmission efficiency is improved, but the circuit complexity increases
Solution Approach 1:
The data transmission process is segmented into multiple phases using non-overlapping latch control signals. Data blocks are divided and transmitted in parallel through different channels, with each channel controlled by a specific phase of the latch control signals. This segmentation enables efficient parallel processing while using a systematic approach to signal generation.
Solution Approach 2:
The latch control circuit generates periodic non-overlapping latch control signals that cycle through different phases. This periodic action coordinates the parallel arrangement and transmission of data blocks, ensuring that each data block is latched at the appropriate time without conflict, thereby achieving high-speed data transmission.
Data Source
AI summary
A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.