Source Driver Line Pair Blocks Reduce Layout Area
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Solution Overview
Problem
The existing source drivers for display devices require a large number of transistors for data inversion driving methods, leading to a significant layout area due to the separate layouts of positive and negative decoders, which complicates the sharing of data lines and increases the complexity of the circuit.
Innovation Solution
The source driver incorporates line pair driving blocks that operate adjacent data lines, featuring a control block to generate loading and polarity control signals, de-multiplexing latches, decoding portions with positive and negative decoders, and multiplexing amplifiers to generate gradation voltages, reducing the number of elements and layout area by sharing digital data and controlling polarity effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data inversion driving method is implemented with separate positive and negative decoders, then polarity switching for pixels is achieved, but layout area and device complexity increase significantly
Solution Approach 1:
The patent merges the positive decoder and negative decoder into a single shared decoder structure. The same decoder circuit is used to generate both positive and negative polarity gradation voltages by controlling the switching of pixel electrodes, eliminating the need for separate decoder layouts and reducing overall layout area while maintaining full polarity switching capability.
Solution Approach 2:
The decoder is designed with universal functionality to handle both positive and negative polarity operations. By using a single decoder that can selectively generate different polarity voltages through control signals, the system achieves multi-functionality, allowing one decoder to replace what would traditionally require two separate decoders, thus reducing layout area.
2Adaptability or versatility
If separate positive and negative decoders are used for data inversion driving, then polarity control is achieved, but device complexity and number of transistors increase
Solution Approach 1:
The patent combines the positive decoder and negative decoder into one shared decoder unit. This merging reduces the total number of transistors required, as the same decoding logic and circuit elements are reused for both polarity operations, rather than duplicating the entire decoder structure for positive and negative polarities separately.
Solution Approach 2:
The single decoder is designed to perform multiple functions by generating both positive and negative polarity control signals through selective switching. This universal decoder handles all decoding operations for both polarities, reducing device complexity by eliminating redundant transistor circuits that would exist in separate decoder implementations.
3Area of stationary object
If two data lines are shared by positive and negative decoders, then layout area is reduced, but circuit complexity and data line management increase
Solution Approach 1:
The patent merges the data line usage into a unified structure where a single set of data lines serves both positive and negative decoder operations. By sharing the same data lines and control signals for both polarity operations, the layout area is reduced while the unified control mechanism manages the increased circuit complexity through centralized signal distribution.
Data Source
AI summary
A source driver for display devices includes line pair driving blocks. Each of the line pair driving blocks includes a de-multiplexing portion for de-multiplexing first and second digital data to generate first and second de-multiplexing data, a decoding portion for decoding the first and second de-multiplexing data to generate first and second analog data, and a multiplexing portion for multiplexing the first and second analog data to generate first and second gradation voltages. In the source driver, the de-multiplexing portion is controlled by signals having information of loading timing for the digital data and information of polarity for the gradation voltages.


