Source Driver IC Synchronization via Lock Signal
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Solution Overview
Problem
In display devices, asynchronous data recognition between the timing controller and source driver ICs leads to inaccurate processing, degrading image quality due to unsynchronized data transmission.
Innovation Solution
Implementing a synchronization mechanism where the controller transmits a lock signal with an internal clock to the source driver ICs, ensuring that data is synchronized to the internal clock before transmission to the controller, using analog-to-digital converters to convert sensing data, and grouping source driver ICs for efficient signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is transmitted asynchronously between the timing controller and source driver ICs, then device complexity is reduced, but data recognition accuracy deteriorates leading to image quality degradation
Solution Approach 1:
The patent introduces a lock signal as an intermediary carrier that transports the internal clock from the timing controller to the source driver ICs. This lock signal mediates the synchronization between transmitter and receiver without requiring complex dedicated clock distribution wiring, thereby maintaining data recognition accuracy while avoiding excessive device complexity
Solution Approach 2:
The lock signal serves multiple functions simultaneously: it acts as a control signal for level conversion, carries the internal clock for synchronization, and provides timing reference for data transmission. This multi-functionality eliminates the need for separate dedicated clock lines and control signals, resolving the contradiction between synchronization accuracy and system complexity
2Speed
If sensing data is transmitted without synchronization, then transmission speed is increased, but data processing reliability deteriorates due to asynchronous state errors
Solution Approach 1:
The patent performs preliminary synchronization by embedding the internal clock in the lock signal before data transmission begins. The source driver ICs use this pre-established timing reference to synchronize their data output, ensuring reliable processing without requiring post-transmission synchronization corrections that would slow down the system
3Device complexity
If the controller recognizes data using its internal clock without synchronization, then device complexity is reduced, but manufacturing precision deteriorates due to asynchronous data recognition
Solution Approach 1:
The lock signal acts as an intermediary that carries the internal clock timing information to the source driver ICs. This allows the data transmission to be synchronized to the controller's internal clock without requiring the controller to directly generate or distribute complex clock signals, maintaining timing precision while keeping the system simple
Solution Approach 2:
Instead of the controller directly generating and distributing clock signals to synchronize data reception, the patent inverts the approach by having the controller embed its internal clock in a data signal (lock signal) that is then used by the source drivers to synchronize their own output. This indirect synchronization method achieves the same timing accuracy with reduced complexity
Data Source
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AI summary
The present invention relates to a controller, a source driver integrated circuit (IC), a display device, and a signal transmission method thereof. To provide a display device and a method for signal transmission in a display device, which are able to provide sensing data to the controller in a synchronized manner to allow the controller to recognize the sensing data reliable a display device is provided comprising: display panel (110) having data lines (DL) and gate lines (GL), wherein subpixels are disposed at intersections of the data lines (DL) and gate lines (GL); at least one source driver integrated circuit (SDIC) for supplying data signals to the data lines (DL) and receiving sensing data from a subpixel; at least one gate driver integrated circuit (GDIC) for supplying scanning signals to the gate lines (GL); a controller (140) for controlling the source driver IC (SDIC #k) and the gate driver IC (GDIC); an analog/digital converter, ADC, for receiving the sensing data of the subpixel and for converting the sensing data to a digital data and outputting the digital data to the controller (140), wherein the controller (140) is adapted to provide timing information to the source driver IC (SDIC) for adjusting in the source driver IC the timing for outputting of the digital data to the controller (140), and wherein the controller (140) is adapted to perform a compensation based on the received digital data.