Source Driver IC Offset Cancellation in Low Power Mode

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Solution Overview

Problem

Display devices face output offset issues between source driver ICs when operating in low-power mode due to the lack of clock signal reception, leading to incomplete offset cancellation and potential image data retention.

Innovation Solution

A source driver IC and timing controller configuration that allows for separate clock signal reception and boosting, enabling offset cancellation even in low-power mode without additional transmission lines, thereby simplifying device configuration and reducing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the timing controller turns off the transmission circuit to operate in low-power mode, then power consumption is reduced, but the source driver IC cannot receive the clock signal and fails to perform output offset cancellation

Engineering Contradiction:

Improvepower consumptionVSAvoidoutput offset cancellation

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent separates the clock signal transmission function from the data transmission function by providing a dedicated clock signal line that operates independently from the main data transmission circuit. This allows the transmission circuit to be turned off for power saving while the clock signal continues to be supplied for offset cancellation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The clock signal line serves multiple functions: it provides clock signals during normal operation and continues to enable offset cancellation during low-power mode. This multi-functionality allows the system to maintain reliability while reducing power consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a separate clock signal line is added for low-power mode operation, then output offset cancellation is maintained, but device complexity increases

Engineering Contradiction:

Improveoutput offset cancellationVSAvoidtransmission circuit configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock signal transmission with the existing transmission infrastructure by using a dedicated line that integrates with the current system architecture. This approach adds minimal complexity while maintaining offset cancellation functionality.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If additional transmission lines are added for clock signal reception, then offset cancellation is enabled in low-power mode, but manufacturing cost increases

Engineering Contradiction:

Improveoffset cancellation capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the transmission functions by dedicating specific lines for clock signal transmission, allowing the system to maintain offset cancellation while using existing transmission infrastructure, thereby minimizing additional manufacturing costs.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12170051B2Source driver integrated circuit, method of driving the same, and timing controller

Publication Date: 2024.12.17 LX SEMICON CO LTD

AI summary

A source driver IC capable of cancelling an output offset is provided. The source driver IC comprises a reception circuit configured to receive an input data packet from a timing controller when operating in a normal mode and obtain an image data and a first clock signal from the input data packet, a control circuit configured to receive and output the image data and the first clock signal from the reception circuit when operating in the normal mode. The control circuit is configured to receive and output a second clock signal from the timing controller when operating in a low power mode. The source driver IC further comprises an output buffer circuit configured to output a data voltage related to the image data when operating in the normal mode and maintain an output of the data voltage when operating in the low power mode.