Source Driver Transistor Matching for Offset and Yield Control
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Solution Overview
Problem
Existing source drivers for LCD panels face challenges in achieving uniform output voltage due to offset characteristics caused by transistor mismatches during the fabrication process, leading to increased development time and cost with empirical design revisions.
Innovation Solution
A method is introduced to design a driver by matching transistors in critical stages, interpreting offset voltages using current changes, and adjusting transistor sizes to minimize offset, with a simulation-driven approach to achieve targeted yield and optimize chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If empirical approaches are used to improve output characteristics, then output uniformity may be improved, but development time and cost increase due to repetitive design revisions
Solution Approach 1:
The patent performs preliminary characterization of transistor mismatch during the design phase by measuring and analyzing offset voltage distributions. This preliminary action enables prediction of output uniformity before fabrication, allowing designers to optimize transistor sizing and matching strategies in advance, thereby avoiding repetitive design revisions and reducing development time while maintaining output uniformity
Solution Approach 2:
The patent implements a feedback mechanism where measured offset voltage data from transistor matching stages is fed back into the design optimization process. By using statistical analysis of mismatch characteristics and adjusting transistor dimensions based on this feedback, the design achieves improved output uniformity without requiring multiple iterative fabrication cycles, thus reducing development time and cost
2Manufacturing precision
If transistor matching is improved to reduce offset voltage, then output characteristics improve, but chip area increases
Solution Approach 1:
The patent systematically varies transistor dimension parameters (width, length, area) to find the optimal balance between offset voltage reduction and chip area utilization. By changing these parameters and analyzing their impact on mismatch characteristics through statistical modeling, the design achieves improved offset characteristics with minimal area penalty, avoiding excessive transistor sizing that would unnecessarily increase chip area
Solution Approach 2:
The patent applies enhanced transistor matching strategies selectively to critical matching stages where offset voltage has the most significant impact on output uniformity, rather than uniformly increasing all transistor sizes. This localized approach to quality improvement focuses resources on the most impactful areas, achieving better offset characteristics without proportionally increasing overall chip area
3Productivity
If more buffers are added to increase driver output capacity, then driving capability improves, but offset variation across buffers increases
Solution Approach 1:
The patent adjusts transistor dimension parameters in buffer stages to account for the statistical accumulation of mismatch effects across multiple buffers. By modifying transistor sizes and matching configurations based on the number of buffers required, the design maintains consistent output voltage characteristics even as driver output capacity increases, preventing degradation of voltage consistency
Data Source
AI summary
A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the results of interpreting of the offset, and the size may be adjusted until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield. The resulting determined size may be used to fabricate the driver, to obtain a test yield of the manufactured driver. If the test yield is not the targeted yield, the measured matching information may be adjusted until the adjusted yield of the driver obtained by the simulation approximates the test yield. Therefore, the offset of the driver may be minimized, making it possible to improve output characteristics of the driver, optimize the area, improve the yield, reduce the frequency of revisions in the development of the chip, and/or shorten the period of the chip design.