Source Driver Simultaneous Test Circuit for Multi-Channel DDIs

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Solution Overview

Problem

The increasing number of channels in display driver integrated circuits (DDIs) leads to a proportional increase in electrical die sorting (EDS) test time, necessitating a need for methods to reduce this testing time.

Innovation Solution

A source driver and display driver integrated circuit (DDI) configuration that allows simultaneous testing by utilizing a gamma voltage generator to output varying voltage levels and a comparator to compare these voltages with a reference voltage, along with a level shifter to generate output signals, thereby reducing test time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of channels in DDI is increased to provide more visual information, then the functionality and versatility of the display system is improved, but the EDS test time increases significantly

Engineering Contradiction:
Improvenumber of channelsVSAvoidEDS test time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the testing process into two distinct modes: a first mode for testing the source driver and a second mode for testing the DDI. By dividing the monolithic testing approach into separate test sequences, the system can efficiently test multiple channels without proportionally increasing total test time. The segmentation allows targeted testing of specific functional blocks in optimized timeframes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic testing by switching between different operating modes (first mode and second mode) depending on which component is being tested. The system dynamically adjusts its test configuration and sequence based on the testing requirements, allowing flexible optimization of test time for different channel configurations without requiring separate dedicated test equipment for each scenario.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the EDS test process is performed on source driver and DDI separately, then the measurement precision for each component is improved, but the total test time increases

Engineering Contradiction:
Improvedefect detection accuracyVSAvoidtotal test time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges the testing of the source driver and DDI into a unified integrated test process. By combining both tests within a single test system that can operate in different modes, the patent achieves simultaneous testing of multiple components without compromising the measurement precision that would be obtained from separate dedicated tests. The integrated approach eliminates redundant setup and teardown operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal test system capable of performing multiple functions: it can test the source driver in a first mode and test the DDI in a second mode. This multi-functional testing apparatus maintains high measurement precision for both components while reducing total test time by eliminating the need for separate specialized test equipment and procedures for each component.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12620328B2Source driver reducing test time by simultaneously performing test on the source driver and display driver integrated circuit including the same
Publication Date: 2026.05.05 SAMSUNG ELECTRONICS CO LTD
  • US12620328B2 patent drawing
  • US12620328B2 patent drawing
  • US12620328B2 patent drawing

AI summary

A display driving integrated circuit includes: a gamma voltage generator outputs a plurality of gamma voltages at a first voltage level based on a first control signal in a first time period among a plurality of time periods, outputs a plurality of gamma voltages at a second voltage level based on a second control signal in a second time period among the plurality of time periods, and outputs a reference voltage that swings between a third voltage level lower than the first voltage level and a fourth voltage level higher than the second voltage level in the plurality of time periods; and a source block circuit receives input data in response to a first clock signal in the first time period, selects a first gamma voltage among the plurality of gamma voltages of the first voltage level based on the input data, and compares the first gamma voltage and the reference voltage.