Source Driver Shift Register with Two-Phase Clocking for Holding Margin
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Solution Overview
Problem
Conventional shift register circuits in source drivers for flat panel displays face issues with insufficient holding margin during short shift register clock periods, leading to unstable operation and high current consumption due to continuous latching of the same data.
Innovation Solution
A shift register circuit design that uses two clock signals with different phases and twice the period of the shift register clock signal, where odd and even shift registers are driven by the first and second clock signals respectively, ensuring stable shifting operations and reducing current consumption by controlling the clock signals only for active shifting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the period of the shift register clock signal is shortened to increase operating speed, then productivity is improved, but the holding margin for the horizontal start signal becomes insufficient and the circuit becomes unstable
Solution Approach 1:
The shift register circuit is divided into multiple stages (first shift register stage, second shift register stage, third shift register stage) that process signals sequentially. Each stage has dedicated flip-flops and logic gates that operate in a coordinated sequence, allowing the circuit to maintain stable operation at high clock speeds by breaking down the overall shifting operation into manageable segments with appropriate timing margins at each stage.
Solution Approach 2:
The circuit performs preliminary actions by pre-charging nodes and pre-positioning signals before the actual clock edge arrives. The logic gates are configured to prepare the horizontal start signal and intermediate signals in advance, ensuring that when the clock signal transitions, all signals are ready to be latched reliably even with short clock periods.
2Reliability
If two flip-flops are used per shift register to increase holding margin, then reliability is improved, but the circuit size and complexity increase
Solution Approach 1:
The shift register is segmented into multiple functional stages, with each stage containing flip-flops and associated logic gates. This segmentation allows the circuit to achieve sufficient holding margin through the distributed architecture rather than requiring redundant flip-flops in each individual register unit, thereby maintaining相对较低的 complexity while improving reliability.
Solution Approach 2:
Intermediate signals and logic gates serve as mediators between the horizontal start signal and the final output signals. These intermediary elements process and condition signals at each stage, providing the necessary timing margins and signal integrity without requiring additional flip-flops, thus achieving reliability improvement with minimal increase in circuit complexity.
3Ease of operation
If clock signals are continuously provided to all flip-flops, then ease of operation is improved, but current consumption increases due to continuous latching
Solution Approach 1:
Clock signals are provided periodically rather than continuously to the flip-flops. The circuit is designed so that clock signals are applied only during the specific periods when shifting operations are actually performed. During idle periods when no shifting is needed, clock signals are suspended, preventing unnecessary latching operations and significantly reducing dynamic power consumption while maintaining the ability to perform continuous shifting when required.
Data Source
AI summary
A shift register circuit and method includes: a plurality of shift registers configured to generate latch clock signals by sequentially shifting input signals according to first and second clock signals, the first and second clock signals including: periods longer than a shift register clock signal, and phases different from each other, wherein odd shift registers among the plurality of shift registers are configured to be driven by the first clock signal, and wherein even shift registers are configured to be driven by the second clock signal.