Source Driver Voltage Timing for Display Uniformity

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Solution Overview

Problem

Conventional liquid crystal display devices with rectangular display units suffer from luminance non-uniformity due to differences in settling times of data voltages applied to source bus lines, leading to abnormal displays in oddly-shaped displays where the target image is a solid image but displayed as vertical gradation.

Innovation Solution

A display device with a video signal line drive circuit that includes an output circuit and an output control unit to control the application timing of data voltages, allowing for delayed application start times and selective output of data and predetermined voltages to control-target video signal lines, thereby adjusting the charging rates across the display unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data voltages are applied to all source bus lines simultaneously, then the display operation is simple and fast, but the settling times of data voltages differ across bus lines causing luminance non-uniformity and abnormal display

Engineering Contradiction:
Improvedisplay uniformityVSAvoidvoltage application control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source bus lines are divided into multiple groups based on their load characteristics and lengths. Different groups are assigned different voltage application timing, with longer bus lines receiving voltages earlier than shorter bus lines. This segmentation allows each group to be optimized independently, resolving the settling time differences that cause luminance non-uniformity while maintaining a manageable control structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Data voltages are applied to source bus lines in advance of the actual display refresh cycle, with longer bus lines receiving their voltages before shorter bus lines. This preliminary action ensures that all bus lines have sufficient time to settle to their target voltages before the display operation begins, eliminating the luminance non-uniformity caused by differential settling times.

Inventive Principle:
Principle #10Preliminary action

2Speed

If source bus lines with smaller loads have shorter settling times, then the overall display refresh speed is faster, but this creates luminance non-uniformity where edges appear brighter than centers

Engineering Contradiction:
Improvedisplay refresh speedVSAvoiddisplay uniformity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Different source bus lines are assigned different voltage application timings based on their local characteristics, specifically their length and load. Longer bus lines (typically at edges) receive voltages earlier than shorter bus lines (typically at centers). This local quality approach ensures that each bus line has adequate settling time relative to its specific characteristics, achieving both fast refresh and uniform display.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The voltage application timing parameter is varied across different source bus lines based on their load characteristics. By changing the timing parameter dynamically for different bus lines rather than using a uniform timing, the system achieves optimal settling for each bus line while maintaining high refresh speeds overall.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10803825B2Display device and drive method therefor
Publication Date: 2020.10.13 SHARP KK
  • US10803825B2 patent drawing
  • US10803825B2 patent drawing
  • US10803825B2 patent drawing

AI summary

There is provided a display device that can suppress occurrence of abnormal display caused by “differences in the settling time of data voltages” between the positions of source bus lines. An output circuit in a source driver is configured to selectively output data voltages and predetermined voltages (e.g., positive-polarity and negative-polarity gradation voltages corresponding to a gradation value at an intermediate level) other than the data voltages. A display control circuit is provided with a register that holds information identifying source bus lines whose charging rates are to be adjusted; and a charge sharing control unit that outputs charge sharing control signals based on the information held in the register. Based on the charge sharing control signals, the output circuit applies the predetermined voltages, for a certain period, to source bus lines whose charging rates are to be adjusted and then applies data voltages to the source bus lines.