Source Driving Circuit Buffer Amplifier High Frame Rate Charging
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Solution Overview
Problem
As the frame rate of display panels increases, the charging time for each row of sub-pixel units becomes shorter, leading to insufficient charging of sub-pixel units due to voltage drops caused by resistance and parasitic capacitance, resulting in uneven display.
Innovation Solution
A source driving circuit with a buffer amplifier and a switching assembly that adjusts the voltage levels of the driving signals to optimize charging, including a first amplifier with a high-level terminal coupled to a first power signal terminal and a low-level terminal coupled to a second power signal terminal, and a second amplifier with a high-level terminal coupled to a third power signal terminal and a low-level terminal coupled to a fourth power signal terminal, where the voltage of the second power signal terminal is less than the third power signal terminal, and a detection circuit to control the switching assembly based on potential differences between adjacent rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frame rate of the display panel is increased, then the display refresh speed is improved, but the charging time for each row of sub-pixel units becomes shorter leading to insufficient charging
Solution Approach 1:
The patent changes the voltage parameters of the driving signal by using different power signal terminal voltages (VDD1, VDD2, VSS1, VSS2) to increase the voltage amplitude of the driving signal. This allows the pixel units to charge faster within the shortened time period, resolving the contradiction between high frame rate and sufficient charging time.
2Productivity
If the voltage of the driving signal is increased to meet charging requirements, then the charging efficiency is improved, but the power consumption increases
Solution Approach 1:
The patent introduces a switching assembly that dynamically switches between different power signal terminals based on the driving requirements. This allows the circuit to adaptively adjust the voltage levels, achieving high charging efficiency when needed while reducing power consumption during normal operation.
Solution Approach 2:
The patent segments the power supply into multiple independent power signal terminals (VDD1, VDD2, VSS1, VSS2) with different voltage levels. This segmentation allows selective use of different voltage levels for different driving scenarios, optimizing both charging efficiency and power consumption.
3Device complexity
If a traditional single amplifier configuration is used, then the device complexity is low, but the voltage output range is insufficient to meet high frame rate requirements
Solution Approach 1:
The patent divides the single amplifier into two separate amplifiers (first amplifier and second amplifier), each responsible for different voltage output ranges. This segmentation enables the system to achieve a wider voltage output range necessary for high frame rate operation while maintaining manageable circuit complexity.
Solution Approach 2:
The patent combines two amplifiers with different power terminal configurations to create a unified buffer amplifier system that provides extended voltage output range. The switching assembly merges the outputs of both amplifiers to deliver the required driving voltage for high frame rate display.
Data Source
AI summary
A source driving circuit includes a buffer amplifier configured to generate a driving signal from an original driving signal. The buffer amplifier includes a first amplifier and a second amplifier. A high-level terminal of the first amplifier is coupled to the first power signal terminal, a low-level terminal is coupled to the second power signal terminal, and an output terminal is configured to output a positive polarity driving signal. A high-level terminal of the second amplifier is coupled to the third power signal terminal, a low-level terminal is coupled to the fourth power signal terminal, and an output terminal is configured to output a negative polarity driving signal. The voltage of the second power signal terminal is less than the voltage of the third power signal terminal.