Source Driving Circuit Gamma Voltage Response Time
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Solution Overview
Problem
The transmission delay of gamma voltages in source driving circuits due to parasitic capacitances and resistances affects the output slew rate of the output buffer circuit in display devices, impacting the display's image update speed and quality.
Innovation Solution
The source driving circuit incorporates an output buffer circuit with a dual-stage input structure, utilizing a main and auxiliary input stage module with different element sizes to minimize parasitic capacitances during switching periods, allowing for faster gamma voltage transmission and reduced delay, while ensuring stability during stable periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional single-stage input structure is used in the output buffer circuit, then the circuit structure is simple, but the gamma voltage transmission delay is large due to parasitic capacitances and resistances
Solution Approach 1:
The input structure is segmented into two stages: a first input stage with a first transistor and a second input stage with a second transistor. This segmentation allows the gamma voltage to be transmitted through multiple smaller steps, reducing the overall transmission delay caused by parasitic capacitances and resistances in each individual stage.
Solution Approach 2:
The first input stage acts as an intermediary between the gamma voltage source and the second input stage. It pre-charges or pre-discharges the parasitic capacitance before the second stage processes the signal, thereby reducing the transmission delay through the use of an intermediate buffering stage.
2Speed
If element sizes are increased to reduce parasitic capacitances, then the gamma voltage transmission speed improves, but the parasitic capacitances and resistances increase
Solution Approach 1:
Different transistors in the input structure are designed with different element sizes according to their specific functional requirements. The first transistor in the first input stage has optimized dimensions for reducing parasitic capacitance during the initial charging/discharging phase, while the second transistor in the second input stage has dimensions optimized for signal amplification and drive capability, achieving local optimization of performance.
Solution Approach 2:
The patent changes the electrical parameters (width, length, doping concentration) of the transistors in the input stages to optimize the balance between parasitic capacitance and drive capability. By carefully selecting transistor dimensions and doping levels, the design achieves faster switching speeds while controlling parasitic effects.
Data Source
AI summary
A source driving circuit of a display includes a gamma resistor strings, a digital to analog (DAC) circuit, and an output buffer circuit. The output buffer circuit includes input stage module, gain stage module, and output stage module. The input stage module includes main input stage unit and auxiliary input stage unit. Sizes of elements in main input stage unit are larger than sizes of elements in the auxiliary input stage unit, smaller sizes presenting smaller parasitic capacitances. During the switching period, the auxiliary input stage unit, gain stage module, and output stage module form a first unity gain amplifier outputting the driving voltages. During the stable period, the main input stage unit, gain stage module, and output stage module form a second unity gain amplifier outputting the driving voltages. A display device is also disclosed.