Source Field Plate Modulation for HEMT Breakdown Voltage and Frequency Trade-offs
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Solution Overview
Problem
The use of source field plates in semiconductor devices increases breakdown voltage but also increases gate-source capacitance (Cgs), which deteriorates frequency characteristics, such as reducing fT and fMAX, and affects the reliability of High Electron Mobility Transistors (HEMTs).
Innovation Solution
A semiconductor device design that includes a substrate, semiconductor layer, source and drain electrodes, a gate electrode, a dielectric layer with recesses, and a source field plate electrically connected to the source electrode, where the source field plate partially covers the recesses in the dielectric layer, allowing for varying distances from the semiconductor layer surface to reduce Cgs without compromising frequency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If source field plates are used to increase breakdown voltage, then the bearable voltage in the depletion region is improved, but gate-source capacitance Cgs increases which deteriorates frequency characteristics
Solution Approach 1:
The source field plate structure implements local quality by creating different vertical distances between the source field plate and the gate electrode at different horizontal positions. Specifically, the source field plate is positioned at a first vertical distance from the gate electrode at a first horizontal position, and at a second vertical distance from the gate electrode at a second horizontal position. This spatial variation in distance allows different regions of the source field plate to serve different functions: regions closer to the gate provide stronger field effect for breakdown voltage enhancement, while regions farther away contribute less to gate-source capacitance, thus resolving the contradiction between improving breakdown voltage and maintaining frequency characteristics.
2Reliability
If the area of source field plate overlapping the gate electrode is reduced to decrease Cgs, then gate-source capacitance is reduced, but frequency response is delayed and frequency characteristics are affected
Solution Approach 1:
The invention resolves the contradiction by transitioning from a two-dimensional area-based approach to a three-dimensional spatial configuration approach. Instead of simply reducing the overlapping area of the source field plate with the gate electrode, the invention utilizes the vertical dimension by positioning the source field plate at varying vertical distances from the gate electrode at different horizontal positions. This dimensional transformation allows the source field plate to maintain sufficient overlapping area for breakdown voltage enhancement while controlling gate-source capacitance through vertical distance modulation, thereby improving frequency characteristics without sacrificing breakdown voltage.
3Productivity
If electric field lines are congregated at the edge of gate electrode adjacent to drain electrode, then field effect is concentrated, but electric field peak is generated causing increased leakage current and device failure
Solution Approach 1:
The source field plate acts as a counterweight to the electric field peak formed at the gate electrode edge. By positioning the source field plate at optimized vertical distances, it generates an opposing electric field that counterbalances the concentrated field lines at the gate edge, thereby reducing the peak electric field intensity. This counteracting field distribution reduces leakage current and prevents avalanche breakdown, improving device reliability while maintaining the necessary field effect concentration for proper transistor operation.
Solution Approach 2:
The invention implements dynamics by creating a non-uniform, position-dependent vertical distance between the source field plate and the gate electrode. The source field plate is positioned at a first vertical distance at a first horizontal position and at a second vertical distance at a second horizontal position, creating a dynamic field distribution profile. This dynamic configuration allows the electric field to be modulated across different regions, concentrating field lines where needed for productivity while dispersing peak fields to maintain reliability, thus dynamically balancing both requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces gate leakage current, increases breakdown voltage, and improves frequency characteristics, maximizing the high output power of HEMTs by modulating electric field distribution and reducing peak electric field intensity at the gate electrode edge.
Implementation Method 1
distribution of the electric field lines in the depletion region of a barrier layer is modulated by using the field plate
Implementation Method 2
an area of a portion of the source field plate overlapping the gate electrode can be reduced
Implementation Method 3
quantum wells and two-dimensional electron gas with high concentration can be generated near heterojunction interfaces
Implementation Method 4
quantum wells and two-dimensional electron gas with high concentration can be generated near heterojunction interfaces, such two-dimensional electron gas is trapped in the quantum wells
Implementation Method 5
the leakage current of the gate electrode is reduced
Data Source
AI summary
A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path, wherein a part of the source field plate above the gate electrode has a varying distance from an upper surface of the semiconductor layer. A method of manufacturing such a semiconductor device is also disclosed.