Programmable Source Follower Attenuator for Linear Wideband Signals
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Solution Overview
Problem
High-speed serial systems face challenges in managing non-linear distortion of large amplitude input signals due to active device limitations, necessitating an innovative attenuator design that can scale down signal magnitude while meeting wideband requirements.
Innovation Solution
A signal attenuator circuit incorporating a complementary source follower circuit and a programmable gain-tuning array circuit, utilizing transistors and multiplexers to adjust attenuator gain through selective enablement of parallel-connected cells, ensuring linear output and wideband performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large amplitude input signal is received by an active device (e.g., amplifier), then the signal can be processed, but non-linear distortion occurs due to active device limitations
Solution Approach 1:
The attenuator circuit is divided into multiple parallel-connected cells (first cell, second cell, third cell, etc.), each contributing a specific attenuation amount. By selectively enabling different cells through control signals, the total attenuation can be precisely adjusted in discrete steps to achieve the desired signal level without overloading the active device
Solution Approach 2:
The attenuator gain is dynamically adjustable through a programmable gain-tuning array circuit that selectively enables or disables parallel-connected cells based on control signals. This dynamic adjustment allows the system to adapt to different signal amplitudes and maintain optimal performance across varying operating conditions
2Reliability
If signal attenuation is increased to prevent non-linear distortion, then active device performance is protected, but signal magnitude is reduced excessively
Solution Approach 1:
The attenuator provides dynamic gain control by selectively enabling different numbers of parallel cells based on the input signal amplitude. When the input signal is large, more cells are enabled to provide greater attenuation; when the input signal is small, fewer cells are enabled to maintain sufficient signal magnitude, thus dynamically balancing protection and signal strength
Solution Approach 2:
The attenuation parameter is changed in discrete steps by enabling or disabling specific parallel-connected cells. Each cell contributes a predetermined attenuation amount, and by combining different numbers of cells, the total attenuation parameter can be precisely adjusted to match the input signal characteristics, preventing both over-attenuation and under-attenuation
3Device complexity
If a fixed gain attenuator is used, then circuit simplicity is maintained, but adaptability to different signal amplitudes is limited
Solution Approach 1:
The attenuator is segmented into multiple parallel-connected cells, each with a specific attenuation value. This segmentation allows the system to achieve multiple discrete gain levels by selectively enabling different combinations of cells, providing adaptability to different signal amplitudes while maintaining a relatively simple circuit architecture based on repeated modular units
Solution Approach 2:
The parallel-connected cells are designed with identical or similar structures, allowing each cell to serve multiple functions depending on which other cells are enabled. The same cell structure can provide different attenuation contributions based on its position in the parallel array and the activation state of other cells, achieving multi-functionality with minimal structural variation
Data Source
AI summary
A signal attenuator circuit includes a complementary source follower circuit and a programmable gain-tuning array circuit. The complementary source follower circuit includes a first transistor and a second transistor. A control terminal of the first transistor is biased by a first bias voltage and is configured to receive an input signal of the signal attenuator circuit. A control terminal of the second transistor is biased by a second bias voltage and is configured to receive the input signal of the signal attenuator circuit. The first transistor and the second transistor include an N-type transistor and a P-type transistor that are always enabled during a period in which the signal attenuator circuit is in operation. The programmable gain-tuning array circuit is coupled to an output node of the complementary source follower circuit, and includes parallel connected cells, each being selectively enabled to adjust an attenuator gain of the signal attenuator circuit.