Differential Source Follower Buffer for High PSRR and Low ISI

Solution Overview

Problem

Existing buffers face challenges in maximizing performance parameters such as noise rejection, bandwidth, and power consumption, particularly in high-speed analog-to-digital converters, where they suffer from low power supply rejection ratio (PSRR) and feedback-induced memory effects, leading to inter-symbol interference (ISI).

Innovation Solution

A differential source follower-based buffer architecture is introduced, incorporating current steering devices and capacitors to improve PSRR and reduce power consumption, featuring a bias generator for optimal operation and capacitors that couple between inputs and outputs to mitigate ISI and FME.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing buffer architectures are used to provide high bandwidth, then signal propagation speed is improved, but power supply rejection ratio deteriorates

Engineering Contradiction:

ImprovebandwidthVSAvoidpower supply rejection ratio

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The buffer is divided into two separate buffers operating in parallel: a first buffer for transmitting the input signal and a second buffer for rejecting power supply noise. This segmentation allows each buffer to be optimized for its specific function, achieving both high bandwidth and high PSRR simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A capacitor is introduced as an intermediary element coupled between the power supply node and the first buffer. This capacitor acts as a noise filter, blocking power supply noise from affecting the signal path while allowing the buffer to maintain high bandwidth operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If existing buffers are designed for high bandwidth operation, then signal propagation is improved, but inter-symbol interference increases

Engineering Contradiction:

ImprovebandwidthVSAvoidinter-symbol interference

Core Design Contradiction:

SpeedVSObject-generated harmful factors

Solution Approach 1:

A capacitor is introduced as an intermediary element coupled between the power supply node and the first buffer. This capacitor acts as a noise filter, blocking power supply noise from affecting the signal path while allowing the buffer to maintain high bandwidth operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The second buffer provides feedback by actively rejecting power supply noise and feeding this rejection back to the first buffer's power supply node. This feedback mechanism continuously compensates for noise that would otherwise cause inter-symbol interference, enabling high bandwidth operation with reduced ISI.

Inventive Principle:

Principle #23Feedback

3Object-affected harmful factors

If buffer complexity is increased to improve PSRR, then noise rejection is improved, but device complexity increases

Engineering Contradiction:

Improvepower supply rejection ratioVSAvoidbuffer complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The buffer is divided into two separate buffers operating in parallel: a first buffer for transmitting the input signal and a second buffer for rejecting power supply noise. This segmentation allows each buffer to be optimized for its specific function, achieving both high bandwidth and high PSRR simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second buffer serves multiple functions: it actively rejects power supply noise, provides feedback to the first buffer, and can be implemented using the same circuit topology as the first buffer. This multi-functionality reduces overall system complexity while maintaining high PSRR performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11329662B2Differential source follower with current steering devices

Publication Date: 2022.05.10 INTEL CORP

AI summary

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.